Wilco (wilco.dijkstra.delete@this.ntlworld.com) on July 18, 2022 1:15 am wrote:
> Adrian (a.delete@this.acm.org) on July 17, 2022 11:09 pm wrote:
> > Wilco (wilco.dijkstra.delete@this.ntlworld.com) on July 17, 2022 1:16 pm wrote:
> > >
> > > That's not guaranteed at all. Milan is ~6% faster than Altra in real world testing, and Yitian is ~70%
> > > faster than Altra according to these SPEC results. So Genoa will need a 60% speedup over Milan to leapfrog
> > > Yitian. I expect that Genoa with 50% more cores and DDR channels than Milan will be power constrained.
> >
> >
> > Genoa will not be power constrained, because the TDP is 360 W for the 96-core model.
> >
> > At 3.75 W per core, that is a little lower than for Milan, but the difference
> > is small enough to be covered by the improved efficiency of the 5-nm process.
>
> The base frequency is rumoured to be 2.0-2.15GHz, well below the 7763's 2.45GHz. The better
> 5nm process should have enabled a higher base frequency - it seems the frequency had to be
> scaled back due to power. And yes, it probably means water cooling for the 96-core models.
>
> Wilco


According to rumors, there are a lot of clock frequencies specified for Genoa, for different conditions.

Besides the 2.0-2.15GHz base frequency, there is an all-cores-active boost frequency of around 3.05 GHz, a "low-usage" (?) frequency of around 3.5 GHz and a single-core frequency up to 3.7 GHz.

Also according to the leaked benchmarks, Genoa has essentially the same single-core AVX-512 throughput as Intel Sapphire Rapids or Ice Lake Server, with small differences attributable to the differences in single-core turbo clock frequencies.

Therefore, Genoa must also have two 512-bit FMA units per core, like the Intel CPUs.

We do not know how the base frequency for Genoa is specified, but if it would cover the use of AVX-512, that would be enough to explain the lower base frequency compared to AMD Milan.


Some AMD spokeperson has already said something to the effect that their CPUs will not use, like Intel's, separate frequency limits depending on whether the upper parts of the vector units are powered or not, but that their normal algorithm, which adjust continuously the clock frequency depending on temperature, power consumption, CPU load, and so on, will take care to reduce the clock frequency enough when 512-bit AVX-512 instructions are used.

That would be consistent with the base frequency, i.e. when turbo is disabled, remaining constant regardless whether AVX-512 is used or not.