none (none.delete@this.none.com) on July 25, 2022 11:35 pm wrote:
> Bill G (bill.delete@this.g.com) on July 25, 2022 10:06 pm wrote:
> > Adrian (a.delete@this.acm.org) on July 16, 2022 11:19 pm wrote:
> > > for the computations dominated by the use of floating-point numbers or big integer numbers,
> > > the AMD and Intel CPUs remain without competition (except from GPUs).
> >
> > What is it about AMD and Intel CPUs that make them good for computations on big integers? ARM
> > has add, subtract with carry flag instructions (ADC, SBC) and multiply, multiply-accumulate producing
> > the full width product (MULL, MLAL). x86 has similar instructions (ADCX, ADOX, MULX).
>
> I'm not sure what Adrian claim is, but Apple M1 likely is the fastest per clock CPU for GMP.
> See https://gmplib.org/gmpbench

The M1 number is old'ish, and I suspect that GMP on M1 is not as optimized as it could be.
The last time I (very quickly) looked at this, a performance gate was the handling of flags (carry etc) and the GMP ARMv8 code was not exploiting the fact that on M1 (I can't speak to other ARM cores) you can very rapidly move these to and from integers. I sent them an email about this, but who knows when it will become productized?

Like any new architecture, optimization takes time, and the more specialized the code, the longer it takes for all the pieces to line up -- the relevant people have to acquire the relevant CPUs, then have to become familiar with the performance characteristics, then have to figure/learn/disseminate non-obvious tricks, etc.

> What matters (beyond what you wrote) is the number of integer multiplications you can issue
> per clock. For AArch64, you don't have 64x64->128 bit multiply instructions, so you have to
> use more 64x64->64 bit ones (AArch64 has 64x64->64 low and high, so you need 2 such
> instructions; a possibility, not implemented as far as I know, would be to fuse two such
> multiplies).