Adrian (a.delete@this.acm.org) on July 27, 2022 8:15 am wrote:
> dmcq (dmcq.delete@this.fano.co.uk) on July 26, 2022 2:27 pm wrote:
> > Bill G (bill.delete@this.g.com) on July 25, 2022 10:06 pm wrote:
> > > Adrian (a.delete@this.acm.org) on July 16, 2022 11:19 pm wrote:
> > > > for the computations dominated by the use of floating-point numbers or big integer numbers,
> > > > the AMD and Intel CPUs remain without competition (except from GPUs).
> > >
> > > What is it about AMD and Intel CPUs that make them good for computations on big integers? ARM
> > > has add, subtract with carry flag instructions (ADC, SBC) and multiply, multiply-accumulate producing
> > > the full width product (MULL, MLAL). x86 has similar instructions (ADCX, ADOX, MULX).
> >
> > If I wanted the equivalent of the ADCX ADOX instruction on ARM I'd probably
> > go for an instruction that added three integers and produced two integers
> > - the sum and a high part - and not bother with the flags register at all.
>
>
> That is certainly the best instruction from the POV of a software developer.
>
> In general, all the base operations needed to implement big number
> computations have 3 input operands and 2 output operands.
>
> For addition/subtraction, at input you have 2 word operands and
> carry in, while at output you have 1 word result and carry out.
>
> For multiplication, at input you have 2 words that are multiplied and 1 word that is
> added, while at output you have 2 words, for the low and high parts of the product.
>
> For division, at input you have 2 words that are concatenated into the dividend and 1 word
> as the divisor, while at output you have 2 words, the quotient and the remainder.
>
> For an optimal implementation of the big number algorithms, the best
> is for all 5 operands to be arbitrary general-purpose registers.
>
>
> However, most CPU or ISA designers have been reluctant to provide 5 register fields in the instruction
> encoding and/or 5 ports in the register file, so most ISA's use various tricks like implicit registers
> or shared input/output registers, in order to have less than 5 explicit registers per instruction.

MulHigh gives the extra result register and is combined with the previous MulLow instruction.