AVX-512 unfriendly to heter-performance cores

By: Paul A. Clayton (paaronclayton.delete@this.gmail.com), August 2, 2022 1:19 pm
Room: Moderated Discussions
Adrian (a.delete@this.acm.org) on August 1, 2022 1:45 am wrote:
[snip]
> While 2 kB is not a small size for the architecturally-visible registers,

I think I need better sleep. I derived 8 KiB from 32 (register count) being two to the five and thinking 64 (byte size of each register) was two to the eight!

> I cannot believe
> that this size can cause any serious implementation difficulties in small cores.

Of course, "small" is relative. x86-64 is already problematic for scalar microcontrollers because of the legacy instruction encoding, so that degree of smallness should probably just be ignored. (On the other hand, at that scale the extra percentage of chip area and even low-power-mode power spent on such a core may be modest even for a moderate-performance smart phone chip.)

> Already 40 years ago, there were RISC CPUs with an architectural register file only a few times
> smaller, e.g. of 512 B, even if they were using millions times less transistors per CPU core.
>
> A modern CPU has more register file ports, but AVX-512 does not need more ports than the ISAs with a smaller
> register file, because this is one of the main advantages of using wider registers, i.e. that increasing
> the register width increases the throughput without requiring additional register file ports.

(And, of course, one can get by with one port if execution width is 25% of access width.)

> Moreover, all the resources related to register renaming and to any other parts of the
> CPU control depend on the number of registers, i.e. 32, and not on their width.

Well, the extra rename registers do increase area and power. (It seems that the tricks for reducing area for speculatively dead values and for not yet present values — e.g., virtual physical registers — would be particularly attractive for 64-byte registers. For data level parallelism in general, state retention management and data routing would seem to be friendly to optimization.)

> 32 registers for the FPU, besides the general-purpose registers, have been used
> in a very large number of CPUs for many decades, most of them being many orders
> of magnitude less complex than the smallest cores of today, such as Cortex-A510.
>
> So I do not buy the argument that implementing 32 wide registers can cause any difficulties. There
> are many other features which influence the core complexity much more, and they can be removed from
> a small core without affecting ISA compatibility and the number and size of the visible registers.

Are you using "core complexity" as a proxy for logic area/power? Design effort is not a factor I was considering (as it does not apply much to register size).

> Now that is too late to be changed, but if Intel would have ever believed that the size of the
> registers matters, it would have been very easy to provide a couple of CPUID bits with the implemented
> register width, e.g. 128/256/512, allowing the software to use the corresponding AVX-512 subset
> of instructions, which would have been much better than falling back to AVX.

Of course, if one does not demand software compatibility, the number of registers could also have been kept as 16 ('wasting' code space by supporting 5-bit identifiers).

I think most people feel Intel did not handle AVX-512 well. Mask and scatter-gather support would make vectorization easier (though I was under the impression that scatter-gather is still not [much?] better than scalar loads), so it seems that providing such would help smaller storage ISA variants (and might encourage compiler work to exploit such features as they would be more broadly available — not limited to the data-crunching-monster processors).

> I think that from their actions (e.g. the backporting of some instructions from AVX-512 encoding
> to AVX encoding, and earlier of some from AVX encoding to SSE encoding) it results that the main
> problem with implementing AVX-512 is extending the instruction decoders with the support of another
> set of encoding formats and not the implementation of more or wider registers.

Perhaps if something like your suggested "reduced storage AVX" had been implemented (and AVX-512 non-size functionality had been broadly implemented), backporting would not have been even considered.
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Yitian 710 anonymous22021/10/20 08:57 PM
  Yitian 710 Adrian2021/10/21 12:20 AM
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                    Yitian 710 Adrian2022/07/17 11:09 PM
                      Yitian 710 Wilco2022/07/18 01:15 AM
                        Yitian 710 Adrian2022/07/18 02:35 AM
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            Computations on Big IntegersBill G2022/07/25 10:06 PM
              Computations on Big Integersnone2022/07/25 11:35 PM
                x86 MUL 64x64 Eric Fink2022/07/26 01:06 AM
                  x86 MUL 64x64 Adrian2022/07/26 02:27 AM
                  x86 MUL 64x64 none2022/07/26 02:38 AM
                    x86 MUL 64x64 Jörn Engel2022/07/26 10:17 AM
                      x86 MUL 64x64 Linus Torvalds2022/07/27 10:13 AM
                        x86 MUL 64x64 2022/07/28 09:40 AM
                        x86 MUL 64x64 Jörn Engel2022/07/28 10:18 AM
                          More than 3 registers per instruction-.-2022/07/28 07:01 PM
                            More than 3 registers per instructionAnon2022/07/28 10:39 PM
                            More than 3 registers per instructionJörn Engel2022/07/28 10:42 PM
                              More than 3 registers per instruction-.-2022/07/29 04:31 AM
                Computations on Big IntegersBill G2022/07/26 01:40 AM
                  Computations on Big Integersnone2022/07/26 02:17 AM
                    Computations on Big IntegersBill G2022/07/26 03:52 AM
                    Computations on Big Integers---2022/07/26 09:57 AM
                  Computations on Big IntegersAdrian2022/07/26 02:53 AM
                    Computations on Big IntegersBill G2022/07/26 03:39 AM
                      Computations on Big IntegersAdrian2022/07/26 04:21 AM
                    Computations on Big Integers in Apple AMX UnitsBill G2022/07/26 04:28 AM
                      Computations on Big Integers in Apple AMX UnitsAdrian2022/07/26 05:13 AM
                        TypoAdrian2022/07/26 05:20 AM
                          IEEE binary64 is 53 bits rather than 52. (NT)Michael S2022/07/26 05:34 AM
                            IEEE binary64 is 53 bits rather than 52.Adrian2022/07/26 07:32 AM
                              IEEE binary64 is 53 bits rather than 52.Michael S2022/07/26 10:02 AM
                                IEEE binary64 is 53 bits rather than 52.Adrian2022/07/27 06:58 AM
                                  IEEE binary64 is 53 bits rather than 52.none2022/07/27 07:14 AM
                                    IEEE binary64 is 53 bits rather than 52.Adrian2022/07/27 07:55 AM
                                      Thanks a lot for the link to the article! (NT)none2022/07/27 08:09 AM
                          TypozArchJon2022/07/26 09:51 AM
                            TypoMichael S2022/07/26 10:25 AM
                              TypozArchJon2022/07/26 11:52 AM
                                TypoMichael S2022/07/26 01:02 PM
                    Computations on Big IntegersMichael S2022/07/26 05:55 AM
                      Computations on Big IntegersAdrian2022/07/26 07:59 AM
                        IFMA and DivisionBill G2022/07/26 04:25 PM
                          IFMA and Divisionrwessel2022/07/26 08:16 PM
                          IFMA and DivisionAdrian2022/07/27 07:25 AM
                      Computations on Big Integersnone2022/07/27 01:22 AM
                    Big integer multiplication with vector IFMABill G2022/07/29 01:06 AM
                      Big integer multiplication with vector IFMAAdrian2022/07/29 01:35 AM
                        Big integer multiplication with vector IFMA-.-2022/07/29 04:32 AM
                          Big integer multiplication with vector IFMAAdrian2022/07/29 09:47 PM
                            Big integer multiplication with vector IFMAAnon2022/07/30 08:12 AM
                              Big integer multiplication with vector IFMAAdrian2022/07/30 09:27 AM
                                AVX-512 unfriendly to heter-performance coresPaul A. Clayton2022/07/31 03:20 PM
                                  AVX-512 unfriendly to heter-performance coresAnon2022/07/31 03:33 PM
                                    AVX-512 unfriendly to heter-performance coresanonymou52022/07/31 05:03 PM
                                  AVX-512 unfriendly to heter-performance coresBrett2022/07/31 07:26 PM
                                  AVX-512 unfriendly to heter-performance coresAdrian2022/08/01 01:45 AM
                                    Why can't E-cores have narrow/slow AVX-512? (NT)anonymous22022/08/01 03:37 PM
                                      Why can't E-cores have narrow/slow AVX-512?Ivan2022/08/02 12:09 AM
                                        Why can't E-cores have narrow/slow AVX-512?anonymou52022/08/02 10:13 AM
                                        Why can't E-cores have narrow/slow AVX-512?Dummond D. Slow2022/08/02 03:02 PM
                                    AVX-512 unfriendly to heter-performance coresPaul A. Clayton2022/08/02 01:19 PM
                                      AVX-512 unfriendly to heter-performance coresAnon2022/08/02 09:09 PM
                                      AVX-512 unfriendly to heter-performance coresAdrian2022/08/03 12:50 AM
                                        AVX-512 unfriendly to heter-performance coresAnon2022/08/03 09:15 AM
                                          AVX-512 unfriendly to heter-performance cores-.-2022/08/03 08:17 PM
                                            AVX-512 unfriendly to heter-performance coresAnon2022/08/03 09:02 PM
                        IFMA: empty promises from Intel as usualKent R2022/07/29 07:15 PM
                          No hype lasts foreverAnon2022/07/30 08:06 AM
                        Big integer multiplication with vector IFMAme2022/07/30 09:15 AM
                Computations on Big Integers---2022/07/26 09:48 AM
                  Computations on Big Integersnone2022/07/27 01:10 AM
                    Computations on Big Integers---2022/07/28 11:43 AM
                      Computations on Big Integers---2022/07/28 06:44 PM
              Computations on Big Integersdmcq2022/07/26 02:27 PM
                Computations on Big IntegersAdrian2022/07/27 08:15 AM
                  Computations on Big IntegersBrett2022/07/27 11:07 AM
      Yitian 710 Wes Felter2021/10/21 12:51 PM
        Yitian 710 Adrian2021/10/21 01:25 PM
    Yitian 710 Anon2021/10/21 06:08 AM
      Strange definition of the word single. (NT)anon22021/10/21 05:00 PM
        AMD Epyc uses chiplets. This is why "strange"?Mark Roulo2021/10/21 05:08 PM
          AMD Epyc uses chiplets. This is why "strange"?anon22021/10/21 05:34 PM
            Yeah. Blame spec.org, too, though!Mark Roulo2021/10/21 05:58 PM
              Yeah. Blame spec.org, too, though!anon22021/10/21 08:07 PM
                Yeah. Blame spec.org, too, though!Björn Ragnar Björnsson2022/07/17 06:23 AM
              Yeah. Blame spec.org, too, though!Rayla2022/07/17 09:13 AM
                Yeah. Blame spec.org, too, though!Anon2022/07/17 12:01 PM
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