Adrian (a.delete@this.acm.org) on August 3, 2022 12:50 am wrote:
> I believe that, taking into account what has been offered during the last decade, it makes sense
> to consider as "small cores" those designed to have a good performance at a power consumption
> of around 0.5 W, e.g. Cortex-A55 or Cortex-A510, as "medium cores", those designed to have a
> good performance at a power consumption of around 2 W, e.g. the various Intel Atom cores and
> Cortex-A78/Cortex-A710, and as "big cores", those designed to have a good performance at around
> 4 W, e.g. the Intel/AMD big cores, the Apple big cores or Cortex-X1/Cortex-X2.
>
>
> Using the above terminology, I believe that there is no difficulty in implementing the execution units required
> by the AVX-512 ISA and its 32 wide registers, even in a "small core", when using an up-to-date CMOS process,
> obviously with the expected trade-off between performance and core area and power consumption.
>
> Taking into account the extreme reluctance of Intel to implement an AVX instruction decoder in the past
> Atom cores, and now an AVX-512 instruction decoder in Gracemont, i.e. even in its medium-sized cores, I
> believe that the huge complexity of decoding the complete x86-64 ISA causes non-negligible overheads on
> all cores that are not "big", and this is the main difficulty that has prevented Intel in achieving ISA
> uniformity like ARM, and not any difficulty in implementing the AVX-512 execution units and registers.

There is another datapoint: AMD, which will only implement AVX-512 on Zen 4, and I am not sure if Zen 4 should be considered "big" or "huge" when compared to "big" Cortex-X1 or even Zen 3.