Detailed investigation of M1 load and store bandwidths from L1 out to DRAM

By: Ganon (anon.delete@this.gmail.com), November 9, 2021 8:02 pm
Room: Moderated Discussions
--- (---.delete@this.redheron.com) on November 9, 2021 1:39 pm wrote:
> I have no idea how many people here read my (ongoing, the public version is only
> version 0.7) exegesis of M1 internals. But those who have read the entire thing
> (all 300+ pages!) will remember an on-going bafflement regarding the L1 cache.
>


Thoroughly enjoyed the read; looking forward to the next update. Regarding
m1 pro/max; seems some things have changed at least according to

https://www.anandtech.com/show/17024/apple-m1-max-performance-review/2

where a single core has >100GB/s all the way from L1 to DRAM; even better
than M1.



Re: intel;

not sure if any of these are related;

https://arxiv.org/pdf/1907.00048.pdf talks about skylake server having non-overlapping accesses
from the cache levels.

Some of Aaron Spink's comments in
https://www.realworldtech.com/forum/?threadid=169910&curpostid=170041

might also be relevant regarding L2 reads effectively bypassing the L1.
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TopicPosted ByDate
Detailed investigation of M1 load and store bandwidths from L1 out to DRAM---2021/11/09 02:39 PM
  Detailed investigation of M1 load and store bandwidths from L1 out to DRAMGanon2021/11/09 08:02 PM
    Detailed investigation of M1 load and store bandwidths from L1 out to DRAM---2021/11/09 10:31 PM
      Please don't use the MT graphsAndrei F2021/11/10 03:13 AM
        Please don't use the MT graphs---2021/11/10 10:26 AM
          Followup for Andrei---2021/11/10 06:43 PM
            Followup for AndreiAndrei F2021/11/11 02:30 AM
              Followup for Andrei---2021/11/11 10:21 AM
                Followup for AndreiChester2021/11/11 03:27 PM
                  Followup for Andrei---2021/11/11 03:57 PM
  Detailed investigation of M1 load and store bandwidths from L1 out to DRAMChester2021/11/09 08:26 PM
    Detailed investigation of M1 load and store bandwidths from L1 out to DRAM---2021/11/09 10:37 PM
      Detailed investigation of M1 load and store bandwidths from L1 out to DRAMChester2021/11/10 03:12 AM
    Detailed investigation of M1 load and store bandwidths from L1 out to DRAMAndrei F2021/11/10 04:12 AM
      Thanks for the dataChester2021/11/10 11:17 AM
        Thanks for the dataAndrei F2021/11/10 01:52 PM
          Thanks for the dataChester2021/11/11 12:16 AM
            Thanks for the dataAndrei F2021/11/11 02:45 AM
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