Thanks for the data

By: Chester (lamchester.delete@this.gmail.com), November 11, 2021 12:16 am
Room: Moderated Discussions
> > Also, this wasn't completely theorizing. When I first tried to measure cache/memory bandwidth by
> > linearly reading an array, I had very inconsistent and unexpectedly low results for Zen 2, but not
> > Zen 3. Aligning loads fixed the problem for Zen 2. It seems like Zen 3 actually has 3x256-bit L1D
> > load ports (but only a 2x256-bit path to the FPU) and was able to absorb the misaligned accesses.
>
> I don't remember what happened on that graph, I looked up the various Zen2 results sets
> and they're all >250GB/s for 256-bit loads. You're right in that it's wrong there but
> it's not the test that is awry, I may have screwed something up when copying things.

> The accesses are all aligned here in all the tests.

Thanks for the clarification! That clears things up - any chance the graph could be corrected?
< Previous Post in ThreadNext Post in Thread >
TopicPosted ByDate
Detailed investigation of M1 load and store bandwidths from L1 out to DRAM---2021/11/09 02:39 PM
  Detailed investigation of M1 load and store bandwidths from L1 out to DRAMGanon2021/11/09 08:02 PM
    Detailed investigation of M1 load and store bandwidths from L1 out to DRAM---2021/11/09 10:31 PM
      Please don't use the MT graphsAndrei F2021/11/10 03:13 AM
        Please don't use the MT graphs---2021/11/10 10:26 AM
          Followup for Andrei---2021/11/10 06:43 PM
            Followup for AndreiAndrei F2021/11/11 02:30 AM
              Followup for Andrei---2021/11/11 10:21 AM
                Followup for AndreiChester2021/11/11 03:27 PM
                  Followup for Andrei---2021/11/11 03:57 PM
  Detailed investigation of M1 load and store bandwidths from L1 out to DRAMChester2021/11/09 08:26 PM
    Detailed investigation of M1 load and store bandwidths from L1 out to DRAM---2021/11/09 10:37 PM
      Detailed investigation of M1 load and store bandwidths from L1 out to DRAMChester2021/11/10 03:12 AM
    Detailed investigation of M1 load and store bandwidths from L1 out to DRAMAndrei F2021/11/10 04:12 AM
      Thanks for the dataChester2021/11/10 11:17 AM
        Thanks for the dataAndrei F2021/11/10 01:52 PM
          Thanks for the dataChester2021/11/11 12:16 AM
            Thanks for the dataAndrei F2021/11/11 02:45 AM
Reply to this Topic
Name:
Email:
Topic:
Body: No Text
How do you spell tangerine? 🍊