By: Andrei F (andrei.delete@this.anandtech.com), November 11, 2021 2:45 am
Room: Moderated Discussions
Chester (lamchester.delete@this.gmail.com) on November 10, 2021 11:16 pm wrote:
> > > Also, this wasn't completely theorizing. When I first tried to measure cache/memory bandwidth by
> > > linearly reading an array, I had very inconsistent and unexpectedly low results for Zen 2, but not
> > > Zen 3. Aligning loads fixed the problem for Zen 2. It seems like Zen 3 actually has 3x256-bit L1D
> > > load ports (but only a 2x256-bit path to the FPU) and was able to absorb the misaligned accesses.
> >
> > I don't remember what happened on that graph, I looked up the various Zen2 results sets
> > and they're all >250GB/s for 256-bit loads. You're right in that it's wrong there but
> > it's not the test that is awry, I may have screwed something up when copying things.
>
> > The accesses are all aligned here in all the tests.
>
> Thanks for the clarification! That clears things up - any chance the graph could be corrected?
Done
> > > Also, this wasn't completely theorizing. When I first tried to measure cache/memory bandwidth by
> > > linearly reading an array, I had very inconsistent and unexpectedly low results for Zen 2, but not
> > > Zen 3. Aligning loads fixed the problem for Zen 2. It seems like Zen 3 actually has 3x256-bit L1D
> > > load ports (but only a 2x256-bit path to the FPU) and was able to absorb the misaligned accesses.
> >
> > I don't remember what happened on that graph, I looked up the various Zen2 results sets
> > and they're all >250GB/s for 256-bit loads. You're right in that it's wrong there but
> > it's not the test that is awry, I may have screwed something up when copying things.
>
> > The accesses are all aligned here in all the tests.
>
> Thanks for the clarification! That clears things up - any chance the graph could be corrected?
Done