By: Kara (karaardalan.delete@this.gmail.com), December 1, 2021 11:32 am
Room: Moderated Discussions
Arm recently updated their main (non-dev) website cortex a710 section,adding merged core with 2 cores per complex to the specifications.
Now if the motivation behind cortex a510 merged cores was to reduce silicone area by making the two cores share a single simd unit with two neon engines, then what implications would a ca710 merged core have?
Since each ca710 already has its own two 128-bit vector lanes, could this mean a merged core complex would have a single simd unit with 4 neon engines?
Maybe we can see merged cortex x_ / neoverse v_ complexes with 8 neon engines and a 1024-bit wide vector register capable of implementing massive yet cost effective SVE2 vector processing.
Now if the motivation behind cortex a510 merged cores was to reduce silicone area by making the two cores share a single simd unit with two neon engines, then what implications would a ca710 merged core have?
Since each ca710 already has its own two 128-bit vector lanes, could this mean a merged core complex would have a single simd unit with 4 neon engines?
Maybe we can see merged cortex x_ / neoverse v_ complexes with 8 neon engines and a 1024-bit wide vector register capable of implementing massive yet cost effective SVE2 vector processing.
