Kara (karaardalan.delete@this.gmail.com) on December 3, 2021 6:01 am wrote:
> Adrian (a.delete@this.acm.org) on December 3, 2021 5:51 am wrote:
> >
> > https://www.nextplatform.com/2021/12/02/aws-goes-wide-and-deep-with-graviton3-server-chip/
> >
> >
>
> L2pc and L3pc same size? Why do companies do this? Is there any Perf benefit I don't know of?
>
> Sounds like a waste of SRAM and cycles

L2 and L3 solve (or at least can solve) different problems.
Of course if they are forced inclusive equal sizes is dumb. But no-ones forcing inclusion.
Look at Apple for a very different philosophy for how to do this.
I bring up Apple because the fact of the DRAM controllers on a separate die (on non-trivial size) hints that AMZ may be doing something similar.

- Apple's SLC/LLC/LC (call it what you will) is essentially a cache IN FRONT OF DRAM rather than a cache on top of L2.

- It is best thought of as part of a massive memory controller, and as part of the memory controller can be used by the memory controller as optimal. For example, rather than having small write queues, the memory controller can flush altered lines out to DRAM on an optimal schedule whenever read and refresh aren't busy.

- As part of the memory controller all DMA hits the SLC automatically (and can sit there, no power cost of write to RAM) if it will be used soon.(This is orthogonal to DDIO in the case of DMA controllers that, for whatever reason, don't want to or can't write to L2 or L1.)

- It acts as a coherence point, and by having extra tags that cover the L2s, is not forced to inclusive, exclusive, or anything else, just the lines play out as they will fighting amongst each other.

Also all indications are this is a V1 part not an N2 part.