By: --- (---.delete@this.redheron.com), May 5, 2022 11:08 am
Room: Moderated Discussions
We frequently see reference to high density vs high performance variants of a process.
My question is: to what extent is this terminology correct. Specifically, what is to stop me creating a SoC that has elements constructed and manufactured according to the HP rules, and others according to the HD rules?
Possible answers:
- the two processes are simply physically incompatible (eg HD creates structures will be destroyed by high temperature processing elements of the HP process)
- the two processes are economically incompatible in that, yes, if you were willing to pay enough and modify the layout of a fab enough, you could rebuild the fab and mix and match as you wished, but we have the fabs we have, laid out the way they are laid out
- the two processes are guidelines, nothing more. The fabs put together a compatible set of rules for HD vs HP, to make things easier for customers. But an ambitious and savvy enough customer could, in fact, mix and match eg HP logic with HD SRAM if that was what they wanted.
I'm trying to get a handle on which of these three options (or something else?) best represents the truth.
My question is: to what extent is this terminology correct. Specifically, what is to stop me creating a SoC that has elements constructed and manufactured according to the HP rules, and others according to the HD rules?
Possible answers:
- the two processes are simply physically incompatible (eg HD creates structures will be destroyed by high temperature processing elements of the HP process)
- the two processes are economically incompatible in that, yes, if you were willing to pay enough and modify the layout of a fab enough, you could rebuild the fab and mix and match as you wished, but we have the fabs we have, laid out the way they are laid out
- the two processes are guidelines, nothing more. The fabs put together a compatible set of rules for HD vs HP, to make things easier for customers. But an ambitious and savvy enough customer could, in fact, mix and match eg HP logic with HD SRAM if that was what they wanted.
I'm trying to get a handle on which of these three options (or something else?) best represents the truth.
Topic | Posted By | Date |
---|---|---|
HD vs HP Process | --- | 2022/05/05 11:08 AM |
HD vs HP Process | Wouter Tinus | 2022/05/05 11:54 AM |
HD vs HP Process | Mark Roulo | 2022/05/05 12:13 PM |
Also ... | Mark Roulo | 2022/05/05 12:14 PM |
Thanks (NT) | blaine | 2022/05/05 12:21 PM |
Also ... | Groo | 2022/05/06 10:03 AM |
HD vs HP Process | --- | 2022/05/05 02:23 PM |
Above my pay grade, but ... | Mark Roulo | 2022/05/05 03:35 PM |
Above my pay grade, but ... | Doug S | 2022/05/06 11:23 AM |
Above my pay grade, but ... | David Hess | 2022/05/07 03:51 PM |
Above my pay grade, but ... | Groo | 2022/05/08 10:17 AM |
Above my pay grade, but ... | David Hess | 2022/05/09 04:27 PM |
AMD Excavator vs. Steamroller metal layers | Dummond D. Slow | 2022/05/06 01:43 PM |
HD vs HP Process | Adrian | 2022/05/05 10:36 PM |
HD vs HP Process | --- | 2022/05/06 01:14 PM |
HD vs HP Process | Adrian | 2022/05/07 12:35 AM |
HD vs HP Process | Doug S | 2022/05/07 09:00 AM |
HD vs HP Process | --- | 2022/05/09 09:35 AM |
HD vs HP Process | --- | 2022/05/09 09:53 AM |
Other aspects | David Kanter | 2022/05/07 11:13 PM |
Other aspects | --- | 2022/05/09 09:06 AM |
HD vs HP Process | David Kanter | 2022/05/07 11:25 PM |
HD vs HP Process | --- | 2022/05/09 09:15 AM |
HD vs HP Process | anon | 2022/05/09 11:23 PM |
Standard cells in Intel 10nm | David Kanter | 2022/05/07 11:54 PM |
Standard cells in Intel 10nm | --- | 2022/05/09 09:26 AM |
Standard cells in Intel 10nm | Adrian | 2022/05/10 01:24 AM |