By: Jan Wassenberg (jan.wassenberg.delete@this.gmail.com), May 18, 2022 10:40 pm
Room: Moderated Discussions
Brett (ggtgp.delete@this.yahoo.com) on May 18, 2022 11:03 am wrote:
> High core count CPU’s are already memory starved, so adding AVX512 is pointless.
> With 5nm CPU’s you can scratch off the HPC market needing AVX512, as you can’t
> feed that many CPU’s much less the doubled bandwidth needs of AVX512 units.
The current #1 in HPC has 1 TB/s per socket. AFAIK the bandwidth of SPR-HBM is not yet known but could be similar. How do we feed those without 512-bit vectors?
> Now all 8 cores are down clocked in response and your net performance uplift of AVX512 is negative.
You might find these results surprising: https://travisdowns.github.io/blog/2020/08/19/icl-avx512-freq.html#summary .
> High core count CPU’s are already memory starved, so adding AVX512 is pointless.
> With 5nm CPU’s you can scratch off the HPC market needing AVX512, as you can’t
> feed that many CPU’s much less the doubled bandwidth needs of AVX512 units.
The current #1 in HPC has 1 TB/s per socket. AFAIK the bandwidth of SPR-HBM is not yet known but could be similar. How do we feed those without 512-bit vectors?
> Now all 8 cores are down clocked in response and your net performance uplift of AVX512 is negative.
You might find these results surprising: https://travisdowns.github.io/blog/2020/08/19/icl-avx512-freq.html#summary .