By: Michael S (already5chosen.delete@this.yahoo.com), May 19, 2022 5:00 am
Room: Moderated Discussions
Charlie Burnes (charlie.burnes.delete@this.no-spam.com) on May 19, 2022 3:11 am wrote:
> -.- (blarg.delete@this.mailinator.com) on May 18, 2022 5:23 pm wrote:
> > Intel doesn't appear to be dropping it on their server SKUs
>
> At Intel’s Investor Day in February 2022, Intel said the Xeon line in 2024 will be split into a
> series of products with only performance cores (P cores) and a different series of products with
> only energy efficient cores (E cores). The E cores are derived from the Atom line and take about
> 1/4 the area of the P cores. The first Xeon with E cores is called Sierra Forest. It seems safe to
> assume that Sierra Forest Xeons will not have AVX-512 and Intel’s 1024-bit Advanced Matrix Extensions
> (AMX). Intel described Sierra Forest as “Power/perf optimized to support high-density, ultra-efficient
> compute for the cloud”. A front-end web server doesn’t need AVX-512 and AMX.
Front-end server also does not need 4x64-bit FMA. But Gracemont core still has it.
From perspective of peak power consumption, reducing number of double-precision FMA EUs from 4 to 2 is bigger gain than absence of EVEX decoders (assuming that under the hood both AVX512 and AVX256 are executed by the same 128-bit EUs).
So, I am pretty sure that real reason for the presence of "overkill" FMA EUs in coming Sierra Forest Xeons is the same as the reason for absence of [narrow implementation of] AVX-512 - limitations of human resources rather than exact needs of front-end web servers.
Good engineers are hard to find, so it makes sense to reuse design done by good engineers for slightly different market than to expect that average engineers will do better due to targeting more focused requirements.
> -.- (blarg.delete@this.mailinator.com) on May 18, 2022 5:23 pm wrote:
> > Intel doesn't appear to be dropping it on their server SKUs
>
> At Intel’s Investor Day in February 2022, Intel said the Xeon line in 2024 will be split into a
> series of products with only performance cores (P cores) and a different series of products with
> only energy efficient cores (E cores). The E cores are derived from the Atom line and take about
> 1/4 the area of the P cores. The first Xeon with E cores is called Sierra Forest. It seems safe to
> assume that Sierra Forest Xeons will not have AVX-512 and Intel’s 1024-bit Advanced Matrix Extensions
> (AMX). Intel described Sierra Forest as “Power/perf optimized to support high-density, ultra-efficient
> compute for the cloud”. A front-end web server doesn’t need AVX-512 and AMX.
Front-end server also does not need 4x64-bit FMA. But Gracemont core still has it.
From perspective of peak power consumption, reducing number of double-precision FMA EUs from 4 to 2 is bigger gain than absence of EVEX decoders (assuming that under the hood both AVX512 and AVX256 are executed by the same 128-bit EUs).
So, I am pretty sure that real reason for the presence of "overkill" FMA EUs in coming Sierra Forest Xeons is the same as the reason for absence of [narrow implementation of] AVX-512 - limitations of human resources rather than exact needs of front-end web servers.
Good engineers are hard to find, so it makes sense to reuse design done by good engineers for slightly different market than to expect that average engineers will do better due to targeting more focused requirements.