By: Jan Wassenberg (jan.wassenberg.delete@this.gmail.com), May 19, 2022 6:45 am
Room: Moderated Discussions
-.- (blarg.delete@this.mailinator.com) on May 19, 2022 6:11 am wrote:
> So 3-4 instructions instead of 1, and you lose a register for holding
> a constant (or load it from memory as I think BZHI supports it).
That's fair. I think today's wider CPUs would not have a problem with that.
We have the same problem in reverse for emulating compressstore on SVE - that's 4 instructions (cnt, whilelt, compact, st1), but seems to be quite fast.
> So 3-4 instructions instead of 1, and you lose a register for holding
> a constant (or load it from memory as I think BZHI supports it).
That's fair. I think today's wider CPUs would not have a problem with that.
We have the same problem in reverse for emulating compressstore on SVE - that's 4 instructions (cnt, whilelt, compact, st1), but seems to be quite fast.