By: Michael S (already5chosen.delete@this.yahoo.com), May 20, 2022 6:29 am
Room: Moderated Discussions
-.- (blarg.delete@this.mailinator.com) on May 19, 2022 6:25 am wrote:
> Charlie Burnes (charlie.burnes.delete@this.no-spam.com) on May 19, 2022 3:11 am wrote:
> > At Intel’s Investor Day in February 2022, Intel said the Xeon line in 2024 will be split into a
> > series of products with only performance cores (P cores) and a different series of products with
> > only energy efficient cores (E cores). The E cores are derived from the Atom line and take about
> > 1/4 the area of the P cores. The first Xeon with E cores is called Sierra Forest. It seems safe to
> > assume that Sierra Forest Xeons will not have AVX-512 and Intel’s 1024-bit Advanced Matrix Extensions
> > (AMX). Intel described Sierra Forest as “Power/perf optimized to support high-density, ultra-efficient
> > compute for the cloud”. A front-end web server doesn’t need AVX-512 and AMX.
>
> It's unlikely Sierra Forrest with use Gracemont. Leaks/details on Crestmont/Skymont
> are pretty thin at the moment, so who knows what they'll have.
> I forgot about the E-core only Xeon, and I wouldn't be surprised if they did or didn't
> adopt AVX-512. But it's likely the P-core future Xeons will keep AVX-512.
>
In case of Sapphire Rapids Intel had no choice. They promised compatible replacement to Xeon Phi to one of important US institutions. I don't remember who it was exactly, but certainly one of those that Intel would be afraid to anger.
But for the future ... I would not be so sure, esp. assuming that Raja Koduri remains the boss.
It seems to me that Koduri believes in heterogeneous computing future, from his perspective too powerful throughput compute engine integrated into CPU core is more of nuisance rather than desirable feature.
> Front end web-servers probably don't need high performance SIMD, but the ISA
> itself could have some uses (I, for one, have a front end webserver doing on-demand
> image manipulation). Note that Gracemont implements AVX2 on 128-bit FPUs.
More so, a couple of them.
The 2nd one is unlikely to be helpful in 99% of front end webserver scenarios. Or, rather the second one is helpful, occasionally, because it is 2nd, but the high-IPC code where it is going to help would be pretty much always scalar, so 128-bitness is excessive.
> Charlie Burnes (charlie.burnes.delete@this.no-spam.com) on May 19, 2022 3:11 am wrote:
> > At Intel’s Investor Day in February 2022, Intel said the Xeon line in 2024 will be split into a
> > series of products with only performance cores (P cores) and a different series of products with
> > only energy efficient cores (E cores). The E cores are derived from the Atom line and take about
> > 1/4 the area of the P cores. The first Xeon with E cores is called Sierra Forest. It seems safe to
> > assume that Sierra Forest Xeons will not have AVX-512 and Intel’s 1024-bit Advanced Matrix Extensions
> > (AMX). Intel described Sierra Forest as “Power/perf optimized to support high-density, ultra-efficient
> > compute for the cloud”. A front-end web server doesn’t need AVX-512 and AMX.
>
> It's unlikely Sierra Forrest with use Gracemont. Leaks/details on Crestmont/Skymont
> are pretty thin at the moment, so who knows what they'll have.
> I forgot about the E-core only Xeon, and I wouldn't be surprised if they did or didn't
> adopt AVX-512. But it's likely the P-core future Xeons will keep AVX-512.
>
In case of Sapphire Rapids Intel had no choice. They promised compatible replacement to Xeon Phi to one of important US institutions. I don't remember who it was exactly, but certainly one of those that Intel would be afraid to anger.
But for the future ... I would not be so sure, esp. assuming that Raja Koduri remains the boss.
It seems to me that Koduri believes in heterogeneous computing future, from his perspective too powerful throughput compute engine integrated into CPU core is more of nuisance rather than desirable feature.
> Front end web-servers probably don't need high performance SIMD, but the ISA
> itself could have some uses (I, for one, have a front end webserver doing on-demand
> image manipulation). Note that Gracemont implements AVX2 on 128-bit FPUs.
More so, a couple of them.
The 2nd one is unlikely to be helpful in 99% of front end webserver scenarios. Or, rather the second one is helpful, occasionally, because it is 2nd, but the high-IPC code where it is going to help would be pretty much always scalar, so 128-bitness is excessive.