Adrian (a.delete@this.acm.org) on May 23, 2022 12:25 am wrote:
> Jörn Engel (joern.delete@this.purestorage.com) on May 22, 2022 11:51 pm wrote:
> >
> > I'm with Linus on this one. Having fast and slow cores
> > is mostly fine. But having cores with fundamentally
> > different behavior is too much pain to be worth it, with embedded systems as a possible exception.
>
>
>
> ARM has designed the much smaller core Cortex-A510 to also support SVE2, like the medium-size
> core Cortex-A710/Neoverse N2 and the large core Cortex-X2, the latter 2 cores having complexities
> comparable with the Gracemont and Golden Cove cores of Alder Lake.
>
> This proves that the heterogeneous ISA that is traditional for the Atom/Core CPU series is
> only due to Intel being either stupid or mean, and not due to any technical necessity.
>
>
> So I agree that it is not the programmers who should work to implement a way to cope with this misfeature
> of the Intel CPUs, but it is Intel who should abandon their evil ways and follow completely the ARM
> Big.Little way, including a uniform ISA, if they have started to go in that direction.
>
> The uniform ISA must not be achieved by disabling features on the small cores, as that has the
> consequences that we have seen with AVX-512, which, much more than a decade after its first
> announcement, is not much closer of being a widespread target for software development.
>
>


Sorry, I have pressed "Post" too early.


In the last paragraph, I have intended to write:

"achieved by not implementing features in the small cores and disabling them in the big cores"