By: Jan Wassenberg (jan.wassenberg.delete@this.gmail.com), May 23, 2022 5:49 am
Room: Moderated Discussions
Michael S (already5chosen.delete@this.yahoo.com) on May 23, 2022 2:32 am wrote:
> Shipping RISC-V hardware with vectors? Or experimental boards?
Here's mention of a supercomputer with 16384 bits: https://github.com/riscv/riscv-v-spec/issues/367
Sifive X280 (https://www.sifive.com/cores/intelligence-x280) has 512-bit vectors which when ganged together via RVV's LMUL=8, result in 4096 bit vectors.
> Shipping RISC-V hardware with vectors? Or experimental boards?
Here's mention of a supercomputer with 16384 bits: https://github.com/riscv/riscv-v-spec/issues/367
Sifive X280 (https://www.sifive.com/cores/intelligence-x280) has 512-bit vectors which when ganged together via RVV's LMUL=8, result in 4096 bit vectors.