Adrian (a.delete@this.acm.org) on June 2, 2022 1:47 am wrote:
> Doug S (foo.delete@this.bar.bar) on June 1, 2022 9:50 pm wrote:
> > Peter Lewis (peter.delete@this.notyahoo.com) on June 1, 2022 3:55 pm wrote:
> > > >> I think x86 will eventually be killed by variable length instruction decode, Moore’s law slowing
> > > >> down, availability of software binary translation from x86 to something else and most low-performance
> > > >> software running on top of JavaScript. The x86 instruction sets will eventually have the same market
> > > >> significance as the IBM 360 instruction set. I own Intel stock and I’m not selling because I think
> > > >> it will take more than 20 years for x86 to be displaced from the dominant position it has today.
> > > >
> > > > Why? What are the market forces that you believe will displace
> > > > x86? What do you think will replace it, RISC-V?
> > >
> > > My guess is the higher complexity and higher power consumption
> > > of x86 will eventually allow ARM implementations
> > > to outperform x86 implementations. Apple’s M1 P-cores currently
> > > decode 8 instructions per clock, while Intel’s
> > > Golden Cove cores in Alder Lake and Sapphire Rapids decode
> > > 6 instructions per clock. When ARM implementations
> > > are decoding 32 instructions per clock, it will be very difficult for x86 implementations to keep up.
> > >
> >
> >
> > People have been predicting this ever since the first superscalar RISCs appeared over 30
> > years ago, and it still hasn't happened. A couple years ago people were saying 3/4 wide was
> > the best x86 could manage, now they've beat it. Are you saying where they are now is the
> > limit, or will the goalposts shift again in 5 years when they take the next step wider?
> >
>
>
>
> Using an ISA that requires a more complex decoder, especially when decoding many
> instructions per cycle, is just one of many factors which determine the relationships
> between speed, power consumption, manufacturing cost, design cost.
>
> A disadvantage in ISA can be easily compensated by advantages in manufacturing
> process or just by having more competent designers.
>
>
> The same happens e.g. in a fighting sport. A heavier fighter has an advantage, put
> a more skilled opponent can easily beat him, despite the weight difference.
>
> Nevertheless, when everything else is the same, so the 2 opponents are equally skilled, the heavier
> will win, which is why all fighting sport competitors are separated in weight classes.
>
>
> The same is in CPU design and manufacturing. When everything else would be equal, the
> CPU using an ISA which needs a simpler decoder would be cheaper and/or faster.

But everything else is not equal. Simpler decoder typically means either
1) worse code density, worse cache hit rate, OR
2) less expressive instructions, more instructions needed to perform the same task.

So the argument "RISC is always better because it allows simpler decoder" is just stupid.

Everything is about tradeoffs. Before 1980's, what mattered was code size. But then, in 1980's simpler decoding allowed pipelining, and the RISCs hype came.

But in 1990's, simple decoding was no longer need for pipelining, but more complex decoding allowed having more expressive instructions(less instructions needed to perform task), and better code density allowed better instruction cache hit rates. But people had gotten stuck to the RISC hype, and did not question it. Every computer architecture course in universities kept preaching the obsolete RISC gospel.

> As long as Intel had other more important advantages, a less efficient ISA did not matter.

Compared to the subject of the previous post, RISC-V, x86 is not "less efficient ISA". It's MORE efficient.

Compared to ARMv9, it could be considered as less efficient, but not because ARM is RISC and does not have instructions which are shorter than 32 bits long. Instead, because ARMv9 has actually been designed to take the best ideas of everything, and take also the new ideas that x86 lacks due it's age and RISC-V lacks due the RISC-purity/RISC-religion.