Anon (no.delete@this.spam.com) on June 2, 2022 2:49 pm wrote:
> Heikki Kultala (heikk.i.kultal.a.delete@this.gmail.com) on June 2, 2022 12:04 pm wrote:
> > Everything is about tradeoffs. Before 1980's, what mattered was code size. But
> > then, in 1980's simpler decoding allowed pipelining, and the RISCs hype came.
>
> Reviewing RISC history I don't think it was simpler decoding that made RISC partical
> in the 80's, but rather simpler design which allowed CPUs to hit market earlier,
> we would be using 68k derivatives had it hit the market one year earlier.
>
> With 80's tech the optimal ISA for those in-order pipelined scalar cores would likely be more
> expressive than RISC because the expressiveness would allow the resources to be used more
> efficiently but far simpler than x86 which wasn't designed with pipeling in mind at all.

A fixed width instruction gives you a couple of things:
1) easier to parallel decode.
2) Don't have to worry about a page fault in the middle of fetching an instruction
(which also means you don't have to worry about both pages being present when you
load in the non-present page and restart).
3) A branch + offset can cover more ground because it addresses "words" not bytes.

Add to this other RISC "rules":
A) No unaligned access, which means a load or store is not going to touch two pages at once.
B) Load/Store architecture: Again, you can only touch one page. Also, the only thing that
needs to restart is a load or a store (i.e. you can't get a floating point exception as well)

Together, I suspect this noticeably simplifies the MMU and page fault service code,
especially in the context of 1980's technology. I would submit, however, that these
are mostly for the convenience of the chip designer and possibly the OS, which in the
end is a false economy (IMNSHO).