By: Adrian (a.delete@this.acm.org), June 2, 2022 11:47 pm
Room: Moderated Discussions
Heikki Kultala (heikk.i.kultal.a.delete@this.gmail.com) on June 2, 2022 12:04 pm wrote:
>
> But everything else is not equal. Simpler decoder typically means either
> 1) worse code density, worse cache hit rate, OR
> 2) less expressive instructions, more instructions needed to perform the same task.
>
In general, you are right about "1)", that would always be true for two ISA encodings designed from scratch.
However, it is not necessarily true when applied to the current x86-64 ISA, which, due to historical reasons, has a much more inefficient encoding than it would have been possible, had it not been constrained by backward compatibility.
AMD has tried to be as less revolutionary as possible, in order to be supported by Microsoft, but a clean encoding, like done by ARM with AArch64, would have been much better.
On the other hand, "2)" is certainly false. It is possible to have very complex instructions, for example vector instructions performing all the operations of typical loops over arrays, including data processing, complex addressing and loop terminating conditions, which have nonetheless very simple encodings.
>
> Compared to the subject of the previous post, RISC-V, x86 is not "less efficient ISA". It's MORE efficient.
>
I completely agree with this.
> Compared to ARMv9, it could be considered as less efficient, but not because ARM is RISC
> and does not have instructions which are shorter than 32 bits long. Instead, because ARMv9
> has actually been designed to take the best ideas of everything, and take also the new ideas
> that x86 lacks due it's age and RISC-V lacks due the RISC-purity/RISC-religion.
>
>
> But everything else is not equal. Simpler decoder typically means either
> 1) worse code density, worse cache hit rate, OR
> 2) less expressive instructions, more instructions needed to perform the same task.
>
In general, you are right about "1)", that would always be true for two ISA encodings designed from scratch.
However, it is not necessarily true when applied to the current x86-64 ISA, which, due to historical reasons, has a much more inefficient encoding than it would have been possible, had it not been constrained by backward compatibility.
AMD has tried to be as less revolutionary as possible, in order to be supported by Microsoft, but a clean encoding, like done by ARM with AArch64, would have been much better.
On the other hand, "2)" is certainly false. It is possible to have very complex instructions, for example vector instructions performing all the operations of typical loops over arrays, including data processing, complex addressing and loop terminating conditions, which have nonetheless very simple encodings.
>
> Compared to the subject of the previous post, RISC-V, x86 is not "less efficient ISA". It's MORE efficient.
>
I completely agree with this.
> Compared to ARMv9, it could be considered as less efficient, but not because ARM is RISC
> and does not have instructions which are shorter than 32 bits long. Instead, because ARMv9
> has actually been designed to take the best ideas of everything, and take also the new ideas
> that x86 lacks due it's age and RISC-V lacks due the RISC-purity/RISC-religion.
>
