Michael S (already5chosen.delete@this.yahoo.com) on June 3, 2022 6:49 am wrote:
> Eric Fink (eric.delete@this.anon.com) on June 2, 2022 10:11 pm wrote:
> > Heikki Kultala (heikk.i.kultal.a.delete@this.gmail.com) on June 2, 2022 12:04 pm wrote:
> >
> > > But everything else is not equal. Simpler decoder typically means either
> > > 1) worse code density, worse cache hit rate, OR
> > > 2) less expressive instructions, more instructions needed to perform the same task.
> > >
> > > So the argument "RISC is always better because it allows simpler decoder" is just stupid.
> >
> > I think though the argument might be (not sure, you guys are the expert) used for ARMv8.
> > It does allow simpler decoding and it doesn't come with a code density disadvantage.
> >
>
> aarch64 code density is very good for a crippled fixed 32-bit instruction words, but it does not quite match
> Thumb2. According to my measurements, it does not even match RV64C, although it's not too far behind.
> [According to my measurements] by now undisputed champ of code density in 32/64-bit world is nanoMIPS.
> Unfortunately, it appears to be dead.

Mill style implied register instructions are far smaller, was expecting such CPU’s to show up by now. Most of the 32 bit instructions in Thumb are loads/stores and using a belt means no register name needed saving 4-5 bits, so most loads/store instructions can be 16 bits.

> > It would be very interesting indeed to get a good measure on how decode
> > complexity actually impacts CPU performance. Not that we every will :)