Doug S (foo.delete@this.bar.bar) on June 2, 2022 11:01 pm wrote:
> I think the simpler decoding was a far bigger deal in the late 80s / early 90s for the advantage of RISC because
> your transistor budget was so much smaller. When you had only a few hundred thousand transistors to play with,
> every one counts in a way that just isn't the case today with tens of billions at your disposal.

Decoding CISC instructions was actually simple, in the first iteration of each CPU family, it was the subsequent iterations that were supposed to do things not thought in the first were things started getting complex, no CISC were thought for one instruction per cycle or parallel decode, and if someone decided to design one such CPU, RISC hit the market earlier.

What I am saying is, it would be possible to design a non-RISC ISA that performs better on 80s technology than RISC actually did, but this would require time and in the 80s time to market was vital, also it would be very hard to implement a ISA designed for 70s tech that outperformed RISC in the 80s.

So, I am talking about an hypothetical ISA.

And 80s RISC was short-sighted too, by implementing features and restrictions that didn't cope well with following iterations.