blaine (myname.delete@this.acm.org) on June 6, 2022 1:51 pm wrote:
> Mark Roulo (nothanks.delete@this.xxx.com) on June 6, 2022 9:56 am wrote:
> > Peter Lewis (peter.delete@this.notyahoo.com) on June 5, 2022 4:23 pm wrote:
> > > > And 80s RISC was short-sighted too, by implementing features and
> > > > restrictions that didn't cope well with following iterations.
> > >
> > > What are some examples of this?
> >
> > Branch delay slots have already been mentioned.
> >
> > Register Windows seem to be another. With good register allocation
> > in the compiler register windows seem to be a bad idea.
> >
> > Predicated instructions may well be a 3rd (especially as the branch predictor gets good).
>
> At HP, RISC was often taken as a religion. Anything can be
> take too far, e.g. SW handled TLB misses on PA RISC.

John Mashey (MIPS) thinks S/W handled TLB is fine :-)

See slide 17 here: https://ucsb-cs154.github.io/w20/lectures/guestlect.pdf

I think only MIPS & HP did this, many thought nuts, but works fine. (P&H) I wrote TLB miss handler, then tuned with minimal hardware for speed CPU had no hardware for finding & accessing Page Tables in memory.

So not *just* HP.