Doug S (foo.delete@this.bar.bar) on June 7, 2022 8:50 am wrote:
> Mark Roulo (nothanks.delete@this.xxx.com) on June 6, 2022 2:18 pm wrote:
> > blaine (myname.delete@this.acm.org) on June 6, 2022 1:51 pm wrote:
> > > Mark Roulo (nothanks.delete@this.xxx.com) on June 6, 2022 9:56 am wrote:
> > > > Peter Lewis (peter.delete@this.notyahoo.com) on June 5, 2022 4:23 pm wrote:
> > > > > > And 80s RISC was short-sighted too, by implementing features and
> > > > > > restrictions that didn't cope well with following iterations.
> > > > >
> > > > > What are some examples of this?
> > > >
> > > > Branch delay slots have already been mentioned.
> > > >
> > > > Register Windows seem to be another. With good register allocation
> > > > in the compiler register windows seem to be a bad idea.
> > > >
> > > > Predicated instructions may well be a 3rd (especially as the branch predictor gets good).
> > >
> > > At HP, RISC was often taken as a religion. Anything can be
> > > take too far, e.g. SW handled TLB misses on PA RISC.
> >
> > John Mashey (MIPS) thinks S/W handled TLB is fine :-)
> >
> > See slide 17 here: https://ucsb-cs154.github.io/w20/lectures/guestlect.pdf
> >
> >

I think only MIPS & HP did this, many thought nuts, but works fine. (P&H) I
> > wrote TLB miss handler, then tuned with minimal hardware for speed CPU had no
> > hardware for finding & accessing Page Tables in memory.

So not *just* HP.
> >
>
>
> OK but consider MIPS and PA-RISC were designed in the 80s when:
>
> - CPUs were much closer to RAM in terms of CPU cycles of access latency
> - CPUs were not decoding and executing up to 6 or 8 instructions per cycle
> - CPUs had such a spartan transistor budget that it absolutely made sense to push whatever you could
> onto software and use those transistors for something else that would help performance more

ARM I think had no virtual memory and SPARC had SW loaded TLB too. I think Alpha also did but that may have been behind PALcode so arguably a better interface but the uarch implementation still a SW loaded TLB. Not sure about the 801/ROMP, maybe it had SW managed segments? So of the pre-90s crop of RISCs, AFAIK none had hardware loaded page tables (anyone have a counter-example?).

Which as you say is fine and likely the right choice for the time. Architecting a hardware TLB reload facility takes little more than specifying page table formats and memory access rules, and small number (possibly one) of additional registers and mode bits to specify page table base and control some MMU operation modes. So it was completely reasonable to leave that out while implementations were doing SW reloading anyway.