By: Anon (no.delete@this.spam.com), June 8, 2022 10:25 am
Room: Moderated Discussions
⚛ (0xe2.0x9a.0x9b.delete@this.gmail.com) on June 8, 2022 8:07 am wrote:
> Register-register MOV instructions in some, but not in all, recent x86 designs are executed early (are
> executed after µop dispatch stage and before µop scheduling stage), so the concrete sequence "MOV reg2
> := reg1; ADD reg2 += [mem]" should have the same effective latency as the hypothetical instruction "ADD
> reg2 := reg1 + [mem]" if the two concrete instructions are dispatched in the same clock cycle.
>
> As far as I know, there is no evidence which would be suggesting that
> there exists an "ADD reg2 := reg1 + [mem]" µop in AMD/Intel CPUs.
None of the above matter, the question here is about code density, not about execution.
> Register-register MOV instructions in some, but not in all, recent x86 designs are executed early (are
> executed after µop dispatch stage and before µop scheduling stage), so the concrete sequence "MOV reg2
> := reg1; ADD reg2 += [mem]" should have the same effective latency as the hypothetical instruction "ADD
> reg2 := reg1 + [mem]" if the two concrete instructions are dispatched in the same clock cycle.
>
> As far as I know, there is no evidence which would be suggesting that
> there exists an "ADD reg2 := reg1 + [mem]" µop in AMD/Intel CPUs.
None of the above matter, the question here is about code density, not about execution.
