Per Hesselgren (perhesselgren.delete@this.yahoo.se) on May 27, 2022 1:07 am wrote:
> ⚛ (0xe2.0x9a.0x9b.delete@this.gmail.com) on May 26, 2022 11:24 am wrote:
> > Heikki Kultala (heikki.kultala.delete@this.gmail.com) on May 26, 2022 11:05 am wrote:
> > > Well, it is not right, because you are ignoring the "over" over and totally
> > > ignoring other things like the much faster multithreaded performance.
> >
> > Just a note: Blender supports AVX-512. It is unclear how much of the Blender performance
> > difference can be attributed to multi-threading and how much to AVX-512.
> >
> > My feeling/impression (but not my conclusion) from AMD's presentation
> > is that Zen4 has an IPC just a few % higher than Zen3.
> >
> > -atom
>
> This is AVX-512 in Zen 4:
>
> Zen 4 on wikichip


Thanks for the link.

So, according to Wikichip, the AVX-512 variant implemented in Zen 4 is that of Ice Lake, to which the extra new instructions of Cooper Lake are added.

The later new instructions of Tiger Lake or Sapphire Rapids are not included. Still, having an Ice Lake equivalent is much better than e.g. a Cascade Lake equivalent.

I wonder how Wikichip has obtained this information.


This information should have been prominently displayed by AMD somewhere on their own site, because it would have been useful for software developers to developers to know it much in advance before the launch of Zen 4, for creating programs optimized for it.