Parsnip (letsallchillout.delete@this.nicecupoftea.com) on May 29, 2022 4:20 am wrote:
> Kara (karaardalan.delete@this.gmail.com) on May 26, 2022 1:52 am wrote:
> > So, is AMD paying everyone to pretend Zen 4 is so awsome? Because Zen 4 numbers look embarrassing.
> > 12% increase in clock speed, 100% increase in L2 cache, and 15% increase in
> > ST perf.? Nah that can't be right, that'd imply Zen 4 is worse, mArch-wise.
> >
> > Or did they pull an Intel/Arm and sacrifice some of the Ex ports for ML pipelines?
> > Or did they pull a cortex A710 and just literally cut off some Ex ports?
> >
>
> Two things stand out:
>
> Cinebench puts no pressure on memory and very little on cache, so
> what useful work does it represent? Not 99% of that I'll wager.
>
> If 15% ST improvement across the board were accurate (as if!) *maybe* they've reached
> a general limit as to what a 3-wide design can achieve? Surely whatever the performance
> is some things are often bumping against the machine width.

What do you mean by "3-wide design" ?

Zen3 can fetch 8 macro-ops from uop cache, it can decode 4 x86 instructions, it can dispatch and rename 6 micro-ops, and issue maybe even 14 micro-ops per cycle.

it can sustain executing 6 simple instruction per cycle from the uop cache, and 4 when not executing from the uop cache.

AFAIK only thing that is limited to 3/cycle in zen3 are scalar integer loads.


Also, any "if 15% is accurate" argumentation is stupid because it's not. AMD has never said that zen has 15% better single-thread performance. AMD has said that is has MORE THAN 15% single-thread performance improvement.