Intel should admit that their implementation of Compute Express Link (CXL) in Sapphire Rapids has some bugs and doesn’t work. Intel should say there is no CXL in Sapphire Rapids and CXL will be included in the next Xeon after Sapphire Rapids, called Emerald Rapids. Instead of being sensible, Intel is saying that CXL has multiple protocols and the protocol needed for cache-coherent access to GPUs and PCIe-attached DRAM is not included in the first implementation. This will cause a lot of confusion about the meaning of CXL support and makes Intel look ridiculous because the main purpose of CXL is cache-coherent access between CPUs, GPUs and PCIe-attached DRAM.

Having 3 CXL protocols and allowing some of them to not be included in some CPUs is making the same type of mistake Intel made with USB 3 naming. There are 3 different speeds of USB 3 (5, 10 and 20 Gbit/s). Instead of naming them USB 3, USB 4 and USB 5, we have names like USB3.2Gen2x2. Intel is repeating this same craziness with CXL by having CXL.io, CXL.cache and CXL.mem. The end result will be that no one will know what it means when a CPU supports CXL.