Crazy CXL Names

By: Michael S (, May 31, 2022 1:21 am
Room: Moderated Discussions
anon2 ( on May 30, 2022 7:19 pm wrote:
> Peter Lewis ( on May 30, 2022 3:54 pm wrote:
> > Intel should admit that their implementation of Compute Express Link (CXL) in Sapphire Rapids has
> > some bugs and doesn’t work. Intel should say there is no CXL in Sapphire Rapids and CXL will
> > be included in the next Xeon after Sapphire Rapids, called Emerald Rapids. Instead of being sensible,
> > Intel is saying that CXL has multiple protocols and the protocol needed for cache-coherent access
> > to GPUs and PCIe-attached DRAM is not included in the first implementation.
> That's exactly what CXL is, that was in the CXL standard from the start.
> > This will cause a lot
> > of confusion about the meaning of CXL support and makes Intel look ridiculous because the main
> > purpose of CXL is cache-coherent access between CPUs, GPUs and PCIe-attached DRAM.
> No. PCI attached memory is not the same as cache coherency. It means it acts
> like a memory controller (that may be used by coherent agents). And so far that
> one is actually the main purpose of it, it has the most useful use cases.
> Cache coherency between CPUs and other masters like GPU or FPGA is the "cool" one that
> everybody seems to think is awesome but so far very little proven use for it. Likely
> Intel only reluctantly started CXL and included it to prevent momentum from building
> behind NVIDIA/IBM/AMD/ARM/etc proposals do to such with their own standards.

Full cache coherence over high-latency link is a horrible, horrible, horrible idea.
Despite what Aaron Spink told me when we were at it last time about cache directory in every Xeon.

And full cache coherence of FPGA-based accelerator is a horrible idea even over moderate-latency link, not just high-latency CXL. Because FPGA itself is high latency.

> >
> > Having 3 CXL protocols and allowing some of them to not be included in some CPUs is making
> > the same type of mistake Intel made with USB 3 naming. There are 3 different speeds of USB
> > 3 (5, 10 and 20 Gbit/s). Instead of naming them USB 3, USB 4 and USB 5, we have names like
> > USB3.2Gen2x2. Intel is repeating this same craziness with CXL by having, CXL.cache and
> > CXL.mem. The end result will be that no one will know what it means when a CPU supports CXL.
> The naming is less stupid than many other names in technology actually. At least CXL.thing
> gives a slightly descriptive name about what it is, WTF is "Emerald Rapids"?
> People will manage. Those who get confused to the point of being unable to even help themselves with
> internet searches are not the people who could possibly do anything useful with the knowledge anyway.

What is ? From the name alone I can't figure out. Going by name it sounds *exactly* the same as normal PCIe.

< Previous Post in ThreadNext Post in Thread >
TopicPosted ByDate
Crazy CXL NamesPeter Lewis2022/05/30 03:54 PM
  Crazy CXL Namesanon22022/05/30 07:19 PM
    Crazy CXL NamesPeter Lewis2022/05/30 09:30 PM
      Crazy CXL Namesanon22022/05/31 02:24 AM
        Crazy CXL NamesPeter Lewis2022/05/31 02:43 AM
          Crazy CXL Namesanon22022/05/31 03:01 AM
            Crazy CXL NamesPeter Lewis2022/05/31 03:36 AM
              Crazy CXL Namesanon22022/05/31 04:32 AM
                Crazy CXL NamesPeter Lewis2022/05/31 05:21 AM
                  Crazy CXL Namesanon22022/05/31 06:03 AM
                    Crazy CXL NamesPeter Lewis2022/05/31 04:27 PM
                      Crazy CXL Namesanon22022/05/31 04:58 PM
                      Crazy CXL Namesgoose2022/05/31 05:35 PM
                        Crazy CXL NamesPeter Lewis2022/06/03 03:10 AM
                          Reason for Crazy CXL NamesGary Kopp2022/06/24 01:43 PM
                            Reason for Crazy CXL Namesdmcq2022/06/25 11:18 AM
                              Reason for Crazy CXL NamesMichael S2022/06/26 01:30 AM
                                Reason for Crazy CXL NamesDummond D. Slow2022/06/26 06:49 AM
                                  Reason for Crazy CXL NamesMichael S2022/06/26 07:32 AM
                                    Reason for Crazy CXL Namesdmcq2022/06/26 11:54 AM
                                Reason for Crazy CXL Namesanon22022/06/26 03:26 PM
                                  Reason for Crazy CXL NamesEric P2022/07/01 02:48 PM
                                    Reason for Crazy CXL Namesanon22022/07/01 07:56 PM
                                      Reason for Crazy CXL NamesGroo2022/07/02 05:13 AM
                                    Reason for Crazy CXL NamesUngo2022/07/01 11:14 PM
                                      Reason for Crazy CXL NamesEric P2022/07/05 03:21 AM
                      Crazy CXL NamesDoug S2022/06/01 12:44 AM
    Crazy CXL NamesMichael S2022/05/31 01:21 AM
      Crazy CXL Namesanon22022/05/31 02:20 AM
      Crazy CXL NamesPeter Lewis2022/05/31 02:24 AM
        Crazy CXL NamesMichael S2022/05/31 03:07 AM
          Crazy CXL NamesPeter Lewis2022/05/31 04:37 AM
            Current NVidia GPU Launch Latency: 10 microsecondsMark Roulo2022/05/31 01:07 PM
              Current NVidia GPU Launch Latency: 10 microsecondsFreddie2022/06/01 09:44 AM
      Crazy CXL Names---2022/05/31 07:56 PM
        Crazy CXL Namesaaron spink2022/05/31 08:32 PM
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