Crazy CXL Names

By: --- (---.delete@this.redheron.com), May 31, 2022 7:56 pm
Room: Moderated Discussions
Michael S (already5chosen.delete@this.yahoo.com) on May 31, 2022 1:21 am wrote:
> anon2 (anon.delete@this.anon.com) on May 30, 2022 7:19 pm wrote:
> > Peter Lewis (peter.delete@this.notyahoo.com) on May 30, 2022 3:54 pm wrote:
> > > Intel should admit that their implementation of Compute Express Link (CXL) in Sapphire Rapids has
> > > some bugs and doesn’t work. Intel should say there is no CXL in Sapphire Rapids and CXL will
> > > be included in the next Xeon after Sapphire Rapids, called Emerald Rapids. Instead of being sensible,
> > > Intel is saying that CXL has multiple protocols and the protocol needed for cache-coherent access
> > > to GPUs and PCIe-attached DRAM is not included in the first implementation.
> >
> > That's exactly what CXL is, that was in the CXL standard from the start.
> >
> > > This will cause a lot
> > > of confusion about the meaning of CXL support and makes Intel look ridiculous because the main
> > > purpose of CXL is cache-coherent access between CPUs, GPUs and PCIe-attached DRAM.
> >
> > No. PCI attached memory is not the same as cache coherency. It means it acts
> > like a memory controller (that may be used by coherent agents). And so far that
> > one is actually the main purpose of it, it has the most useful use cases.
> >
> > Cache coherency between CPUs and other masters like GPU or FPGA is the "cool" one that
> > everybody seems to think is awesome but so far very little proven use for it. Likely
> > Intel only reluctantly started CXL and included it to prevent momentum from building
> > behind NVIDIA/IBM/AMD/ARM/etc proposals do to such with their own standards.
>
> Full cache coherence over high-latency link is a horrible, horrible, horrible idea.
> Despite what Aaron Spink told me when we were at it last time about cache directory in every Xeon.
>
> And full cache coherence of FPGA-based accelerator is a horrible idea even over moderate-latency
> link, not just high-latency CXL. Because FPGA itself is high latency.

Perhaps I'm being very dumb here, but what exactly is the concern? There are multiple cache protocols, and multiple ways to implement them, but in my mental model of the most sensible way to do this, I don't see any obvious reason why you get some sort of generic "everything slows down because of coherency transactions with a slow device" unless there's actual interaction between a CPU and the device (in which case, do you actually get a slowdown compared with the alternative of slow direct writes to the device)?

What am I missing? I guess I have no idea exactly what sort of architecture you are assuming, both in the control case (how things are done today) and in the new case (how you think it would work with cache coherence against a slow cache).

I'm not saying this is a good idea; I'm just saying I don't see where the "everything will slow down by presence of the slow cache" comes from.
< Previous Post in ThreadNext Post in Thread >
TopicPosted ByDate
Crazy CXL NamesPeter Lewis2022/05/30 03:54 PM
  Crazy CXL Namesanon22022/05/30 07:19 PM
    Crazy CXL NamesPeter Lewis2022/05/30 09:30 PM
      Crazy CXL Namesanon22022/05/31 02:24 AM
        Crazy CXL NamesPeter Lewis2022/05/31 02:43 AM
          Crazy CXL Namesanon22022/05/31 03:01 AM
            Crazy CXL NamesPeter Lewis2022/05/31 03:36 AM
              Crazy CXL Namesanon22022/05/31 04:32 AM
                Crazy CXL NamesPeter Lewis2022/05/31 05:21 AM
                  Crazy CXL Namesanon22022/05/31 06:03 AM
                    Crazy CXL NamesPeter Lewis2022/05/31 04:27 PM
                      Crazy CXL Namesanon22022/05/31 04:58 PM
                      Crazy CXL Namesgoose2022/05/31 05:35 PM
                        Crazy CXL NamesPeter Lewis2022/06/03 03:10 AM
                          Reason for Crazy CXL NamesGary Kopp2022/06/24 01:43 PM
                            Reason for Crazy CXL Namesdmcq2022/06/25 11:18 AM
                              Reason for Crazy CXL NamesMichael S2022/06/26 01:30 AM
                                Reason for Crazy CXL NamesDummond D. Slow2022/06/26 06:49 AM
                                  Reason for Crazy CXL NamesMichael S2022/06/26 07:32 AM
                                    Reason for Crazy CXL Namesdmcq2022/06/26 11:54 AM
                                Reason for Crazy CXL Namesanon22022/06/26 03:26 PM
                                  Reason for Crazy CXL NamesEric P2022/07/01 02:48 PM
                                    Reason for Crazy CXL Namesanon22022/07/01 07:56 PM
                                      Reason for Crazy CXL NamesGroo2022/07/02 05:13 AM
                                    Reason for Crazy CXL NamesUngo2022/07/01 11:14 PM
                                      Reason for Crazy CXL NamesEric P2022/07/05 03:21 AM
                      Crazy CXL NamesDoug S2022/06/01 12:44 AM
    Crazy CXL NamesMichael S2022/05/31 01:21 AM
      Crazy CXL Namesanon22022/05/31 02:20 AM
      Crazy CXL NamesPeter Lewis2022/05/31 02:24 AM
        Crazy CXL NamesMichael S2022/05/31 03:07 AM
          Crazy CXL NamesPeter Lewis2022/05/31 04:37 AM
            Current NVidia GPU Launch Latency: 10 microsecondsMark Roulo2022/05/31 01:07 PM
              Current NVidia GPU Launch Latency: 10 microsecondsFreddie2022/06/01 09:44 AM
      Crazy CXL Names---2022/05/31 07:56 PM
        Crazy CXL Namesaaron spink2022/05/31 08:32 PM
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