--- (---.delete@this.redheron.com) on May 31, 2022 7:56 pm wrote:

> Perhaps I'm being very dumb here, but what exactly is the concern? There are multiple cache protocols, and
> multiple ways to implement them, but in my mental model of the most sensible way to do this, I don't see
> any obvious reason why you get some sort of generic "everything slows down because of coherency transactions
> with a slow device" unless there's actual interaction between a CPU and the device (in which case, do you
> actually get a slowdown compared with the alternative of slow direct writes to the device)?
>
> What am I missing? I guess I have no idea exactly what sort of architecture you
> are assuming, both in the control case (how things are done today) and in the new
> case (how you think it would work with cache coherence against a slow cache).
>
> I'm not saying this is a good idea; I'm just saying I don't see where the
> "everything will slow down by presence of the slow cache" comes from.
>

you aren't missing anything. All of these are being implemented with a local filter of some sort (either via directory or snoop cache). As such, unless the cpu needs a line that is actually beyond the filter in a state that needs to be inval'd, there is no issue.