Eric P (eric.delete@this.nospam.com) on July 1, 2022 2:48 pm wrote:
> With PCIe 4, Intel dragged their feet for 7 years because faster PCIe speeds meant fewer servers needed.

What? That makes little sense. There aren't many server customers who are exclusively I/O bound, much less in such a way that the only thing determining how many CPUs they buy is how much PCIe bandwidth each CPU has.

The real reason is something which I remember Intel admitting to a few years ago. It's not a good reason, but understandable.

The glory days of tick-tock led Intel to tie new IO technologies - like PCIe gen 4 - to the latest process nodes only. What's the purpose of designing 14nm PCIe 4 IP when the product roadmap calls for all chips with gen 4 to be 10nm or newer?

If you assume that a new node will ramp to production volume ~every 2 years, that plan works great. But as we all know, 10nm ran into a few snags. Management believed in quick fixes, so they didn't direct engineering to backport 10nm IP like PCIe 4 to 14nm.

Repeat these failures of 10nm process development and management's inability to react to the new post tick/tock reality and that's how you end up with Skylake++++ on 14nm++++ with PCIe 3.0 IO.