By: Adrian (a.delete@this.acm.org), June 13, 2022 1:35 am
Room: Moderated Discussions
Rohit Garg (rohitgarg.delete@this.mac.com) on June 13, 2022 12:59 am wrote:
> David Kanter (dkanter.delete@this.realworldtech.com) on June 12, 2022 7:05 pm wrote:
> > Hi Everyone,
> >
> > Happy Sunday! I am thrilled to bring you my latest article, which focuses on the Intel
> > 4 process that was presented at the VLSI Symposium in Hawaii. Here's a quick summary:
> >
> > The Intel 4 process achieves 20% better performance and scales logic density by 2X while reducing costs
> > through extensive design co-optimization, adoption of new materials, and judicious use of EUV lithography.
> > The first product, the Meteor Lake compute tile will ramp to high volume manufacturing in 2023.
> >
> > Read more here: Intel 4 Process Scales Logic with Design, Materials, and EUV
> >
> > And as always, feel free to discuss or drop questions in this thread!
> >
> > David
> >
>
> In Table 1, is the M1 number for Intel 7 correct?
36 nm is the value shown in the Intel presentation, so it is likely correct.
Not only the M1 pitch is larger for Intel 4, but also the M2 pitch is a little larger.
It is likely that most of the size reduction in the Intel 4 metallization is due to the M0 pitch that is reduced from 40 nm to 30 nm, the same as the fin pitch.
Depending on the gate layout, it is possible that the pitch of the next 4 layers, which have a 50 nm pitch for one direction and a 45 nm pitch for the orthogonal direction, do not affect much the cell size within certain limits, so a smaller pitch for them might have not been worthwhile.
> David Kanter (dkanter.delete@this.realworldtech.com) on June 12, 2022 7:05 pm wrote:
> > Hi Everyone,
> >
> > Happy Sunday! I am thrilled to bring you my latest article, which focuses on the Intel
> > 4 process that was presented at the VLSI Symposium in Hawaii. Here's a quick summary:
> >
> > The Intel 4 process achieves 20% better performance and scales logic density by 2X while reducing costs
> > through extensive design co-optimization, adoption of new materials, and judicious use of EUV lithography.
> > The first product, the Meteor Lake compute tile will ramp to high volume manufacturing in 2023.
> >
> > Read more here: Intel 4 Process Scales Logic with Design, Materials, and EUV
> >
> > And as always, feel free to discuss or drop questions in this thread!
> >
> > David
> >
>
> In Table 1, is the M1 number for Intel 7 correct?
36 nm is the value shown in the Intel presentation, so it is likely correct.
Not only the M1 pitch is larger for Intel 4, but also the M2 pitch is a little larger.
It is likely that most of the size reduction in the Intel 4 metallization is due to the M0 pitch that is reduced from 40 nm to 30 nm, the same as the fin pitch.
Depending on the gate layout, it is possible that the pitch of the next 4 layers, which have a 50 nm pitch for one direction and a 45 nm pitch for the orthogonal direction, do not affect much the cell size within certain limits, so a smaller pitch for them might have not been worthwhile.
