By: Adrian (a.delete@this.acm.org), June 13, 2022 1:50 am
Room: Moderated Discussions
David Kanter (dkanter.delete@this.realworldtech.com) on June 12, 2022 7:05 pm wrote:
> Hi Everyone,
>
> Happy Sunday! I am thrilled to bring you my latest article, which focuses on the Intel
> 4 process that was presented at the VLSI Symposium in Hawaii. Here's a quick summary:
>
> The Intel 4 process achieves 20% better performance and scales logic density by 2X while reducing costs
> through extensive design co-optimization, adoption of new materials, and judicious use of EUV lithography.
> The first product, the Meteor Lake compute tile will ramp to high volume manufacturing in 2023.
>
> Read more here: Intel 4 Process Scales Logic with Design, Materials, and EUV
>
> And as always, feel free to discuss or drop questions in this thread!
>
> David
>
Thanks for the article.
I had already seen most of the Intel slides, but I was wondering about various details, especially about which is the meaning of the "enhanced copper", which has replaced the former cobalt layers. After reading your article, that has become clear enough.
There has been much speculation about whether the choice of cobalt had something to do with the shortcomings of the 10 nm Intel CMOS process. The fact that Intel 4 has reverted to copper, even if with improved linings, seems to confirm that supposition.
The high resistance of the cobalt interconnections is likely to have been one of the reasons for the much too low clock frequencies of Cannon Lake and Ice Lake.
The other serious problem of the 10 nm process, the very low yields, might have been determined mainly by their choices for photolithography, where they have attempted to get very small pitches without using EUV.
> Hi Everyone,
>
> Happy Sunday! I am thrilled to bring you my latest article, which focuses on the Intel
> 4 process that was presented at the VLSI Symposium in Hawaii. Here's a quick summary:
>
> The Intel 4 process achieves 20% better performance and scales logic density by 2X while reducing costs
> through extensive design co-optimization, adoption of new materials, and judicious use of EUV lithography.
> The first product, the Meteor Lake compute tile will ramp to high volume manufacturing in 2023.
>
> Read more here: Intel 4 Process Scales Logic with Design, Materials, and EUV
>
> And as always, feel free to discuss or drop questions in this thread!
>
> David
>
Thanks for the article.
I had already seen most of the Intel slides, but I was wondering about various details, especially about which is the meaning of the "enhanced copper", which has replaced the former cobalt layers. After reading your article, that has become clear enough.
There has been much speculation about whether the choice of cobalt had something to do with the shortcomings of the 10 nm Intel CMOS process. The fact that Intel 4 has reverted to copper, even if with improved linings, seems to confirm that supposition.
The high resistance of the cobalt interconnections is likely to have been one of the reasons for the much too low clock frequencies of Cannon Lake and Ice Lake.
The other serious problem of the 10 nm process, the very low yields, might have been determined mainly by their choices for photolithography, where they have attempted to get very small pitches without using EUV.