By: anonymou5 (no.delete@this.spam.com), June 13, 2022 6:21 am
Room: Moderated Discussions
> There has been much speculation about whether the choice of cobalt had something to do
> with the shortcomings of the 10 nm Intel CMOS process. The fact that Intel 4 has reverted
> to copper, even if with improved linings, seems to confirm that supposition.
>
> The high resistance of the cobalt interconnections is likely to have been one of
> the reasons for the much too low clock frequencies of Cannon Lake and Ice Lake.
Define "much too low".
Sure, e.g. 3.2 for CNL wasn't king of the hill... but for a U part? Not too bad.
The GPU side... was abysmal though...
Also, if Co was a speed limiter, then Intel should have seen that coming. Or are you suggesting their engineers are complete idiots? :)
> The other serious problem of the 10 nm process, the very low yields, might have been determined mainly by their
> choices for photolithography, where they have attempted to get very small pitches without using EUV.
This.
> with the shortcomings of the 10 nm Intel CMOS process. The fact that Intel 4 has reverted
> to copper, even if with improved linings, seems to confirm that supposition.
>
> The high resistance of the cobalt interconnections is likely to have been one of
> the reasons for the much too low clock frequencies of Cannon Lake and Ice Lake.
Define "much too low".
Sure, e.g. 3.2 for CNL wasn't king of the hill... but for a U part? Not too bad.
The GPU side... was abysmal though...
Also, if Co was a speed limiter, then Intel should have seen that coming. Or are you suggesting their engineers are complete idiots? :)
> The other serious problem of the 10 nm process, the very low yields, might have been determined mainly by their
> choices for photolithography, where they have attempted to get very small pitches without using EUV.
This.
