By: Adrian (a.delete@this.acm.org), June 13, 2022 7:32 am
Room: Moderated Discussions
anonymou5 (no.delete@this.spam.com) on June 13, 2022 6:21 am wrote:
> > There has been much speculation about whether the choice of cobalt had something to do
> > with the shortcomings of the 10 nm Intel CMOS process. The fact that Intel 4 has reverted
> > to copper, even if with improved linings, seems to confirm that supposition.
> >
> > The high resistance of the cobalt interconnections is likely to have been one of
> > the reasons for the much too low clock frequencies of Cannon Lake and Ice Lake.
>
> Define "much too low".
>
> Sure, e.g. 3.2 for CNL wasn't king of the hill... but for a U part? Not too bad.
>
> The GPU side... was abysmal though...
Actually I had the CNL NUC, so I have direct experience with it.
The Cannon Lake U CPU was launched simultaneously with Coffee Lake U CPUs, which sustained without problems 4.5 GHz at a similar power consumption with a Cannon Lake U running at 3.2 GHz. I had both NUCs, CNL & CFL, working side to side, so there is no doubt about it.
I define 3.2 GHz when compared to 4.5 GHz as "much too low".
Not much better clock frequency ratios were between Ice Lake and Comet Lake.
I agree that the disabled GPU, running at 0 GHz, qualifies as "abysmal".
>
> Also, if Co was a speed limiter, then Intel should have seen that coming.
> Or are you suggesting their engineers are complete idiots? :)
I completely agree with you that "Intel should have seen that coming".
They should have simulated the 10 nm devices and they should have characterized test structures much in advance of committing to any process technology for 10 nm.
It is more difficult to estimate the future yields in mass production from experiments, but it should not be difficult to estimate with reasonable accuracy the clock frequencies and the power consumption of the devices made with the future technology.
Therefore it is beyond my power of understanding how it was possible for Intel during many years to make only 10 nm devices with significantly worse electrical characteristics than their previous 14 nm devices.
Even now Intel has not recovered completely from the effects of their former erroneous ways, because, for some reason, the improved process technologies used to make Tiger Lake and Alder Lake are sufficiently different from the original 10 nm process, so that it has been too difficult for Intel to migrate their earlier designs to the new process variants.
Because of that, even some of the latest Intel products launched in 2022 (e.g. Ice Lake D, Snow Ridge Refresh, Parker Ridge) or in 2021 (e.g. Ice Lake Server, Jasper Lake, Elkhart Lake) have an abnormally high power consumption. Even if they have a better performance than the older replaced products, the ratio between performance and power consumption is barely better or even worse than for some ancient products from the Broadwell or Skylake generations.
I find it hard to believe that many Intel engineers are complete idiots, but this fiasco cannot be explained otherwise that some have been complete idiots, probably less between the engineers and more between their managers.
> > There has been much speculation about whether the choice of cobalt had something to do
> > with the shortcomings of the 10 nm Intel CMOS process. The fact that Intel 4 has reverted
> > to copper, even if with improved linings, seems to confirm that supposition.
> >
> > The high resistance of the cobalt interconnections is likely to have been one of
> > the reasons for the much too low clock frequencies of Cannon Lake and Ice Lake.
>
> Define "much too low".
>
> Sure, e.g. 3.2 for CNL wasn't king of the hill... but for a U part? Not too bad.
>
> The GPU side... was abysmal though...
Actually I had the CNL NUC, so I have direct experience with it.
The Cannon Lake U CPU was launched simultaneously with Coffee Lake U CPUs, which sustained without problems 4.5 GHz at a similar power consumption with a Cannon Lake U running at 3.2 GHz. I had both NUCs, CNL & CFL, working side to side, so there is no doubt about it.
I define 3.2 GHz when compared to 4.5 GHz as "much too low".
Not much better clock frequency ratios were between Ice Lake and Comet Lake.
I agree that the disabled GPU, running at 0 GHz, qualifies as "abysmal".
>
> Also, if Co was a speed limiter, then Intel should have seen that coming.
> Or are you suggesting their engineers are complete idiots? :)
I completely agree with you that "Intel should have seen that coming".
They should have simulated the 10 nm devices and they should have characterized test structures much in advance of committing to any process technology for 10 nm.
It is more difficult to estimate the future yields in mass production from experiments, but it should not be difficult to estimate with reasonable accuracy the clock frequencies and the power consumption of the devices made with the future technology.
Therefore it is beyond my power of understanding how it was possible for Intel during many years to make only 10 nm devices with significantly worse electrical characteristics than their previous 14 nm devices.
Even now Intel has not recovered completely from the effects of their former erroneous ways, because, for some reason, the improved process technologies used to make Tiger Lake and Alder Lake are sufficiently different from the original 10 nm process, so that it has been too difficult for Intel to migrate their earlier designs to the new process variants.
Because of that, even some of the latest Intel products launched in 2022 (e.g. Ice Lake D, Snow Ridge Refresh, Parker Ridge) or in 2021 (e.g. Ice Lake Server, Jasper Lake, Elkhart Lake) have an abnormally high power consumption. Even if they have a better performance than the older replaced products, the ratio between performance and power consumption is barely better or even worse than for some ancient products from the Broadwell or Skylake generations.
I find it hard to believe that many Intel engineers are complete idiots, but this fiasco cannot be explained otherwise that some have been complete idiots, probably less between the engineers and more between their managers.
