By: Fred Chen (chen.t.fred.delete@this.gmail.com), June 13, 2022 8:38 am
Room: Moderated Discussions
David Kanter (dkanter.delete@this.realworldtech.com) on June 12, 2022 7:05 pm wrote:
> Hi Everyone,
>
> Happy Sunday! I am thrilled to bring you my latest article, which focuses on the Intel
> 4 process that was presented at the VLSI Symposium in Hawaii. Here's a quick summary:
>
> The Intel 4 process achieves 20% better performance and scales logic density by 2X while reducing costs
> through extensive design co-optimization, adoption of new materials, and judicious use of EUV lithography.
> The first product, the Meteor Lake compute tile will ramp to high volume manufacturing in 2023.
>
> Read more here: Intel 4 Process Scales Logic with Design, Materials, and EUV
>
> And as always, feel free to discuss or drop questions in this thread!
>
> David
>
Nice summary, David, thanks.
One thing that surprised me about Intel 7 was that they used SAQP or pitch quartering on layers which I thought only needed SADP or pitch halving. This was gate as well as M0.
Fred
> Hi Everyone,
>
> Happy Sunday! I am thrilled to bring you my latest article, which focuses on the Intel
> 4 process that was presented at the VLSI Symposium in Hawaii. Here's a quick summary:
>
> The Intel 4 process achieves 20% better performance and scales logic density by 2X while reducing costs
> through extensive design co-optimization, adoption of new materials, and judicious use of EUV lithography.
> The first product, the Meteor Lake compute tile will ramp to high volume manufacturing in 2023.
>
> Read more here: Intel 4 Process Scales Logic with Design, Materials, and EUV
>
> And as always, feel free to discuss or drop questions in this thread!
>
> David
>
Nice summary, David, thanks.
One thing that surprised me about Intel 7 was that they used SAQP or pitch quartering on layers which I thought only needed SADP or pitch halving. This was gate as well as M0.
Fred
