By: --- (---.delete@this.redheron.com), June 13, 2022 10:47 am
Room: Moderated Discussions
anonymou5 (no.delete@this.spam.com) on June 13, 2022 6:21 am wrote:
> > There has been much speculation about whether the choice of cobalt had something to do
> > with the shortcomings of the 10 nm Intel CMOS process. The fact that Intel 4 has reverted
> > to copper, even if with improved linings, seems to confirm that supposition.
> >
> > The high resistance of the cobalt interconnections is likely to have been one of
> > the reasons for the much too low clock frequencies of Cannon Lake and Ice Lake.
>
> Define "much too low".
>
> Sure, e.g. 3.2 for CNL wasn't king of the hill... but for a U part? Not too bad.
>
> The GPU side... was abysmal though...
>
> Also, if Co was a speed limiter, then Intel should have seen that coming.
> Or are you suggesting their engineers are complete idiots? :)
>
> > The other serious problem of the 10 nm process, the very
> > low yields, might have been determined mainly by their
> > choices for photolithography, where they have attempted to get very small pitches without using EUV.
>
> This.
Yeah, the cobalt story has always seemed like it omitted something.
TSMC use cobalt for 7nm (and presumably 5nm, though I haven't seen direct evidence of that), and did not appear to have problems.
https://twitter.com/lasserith/status/1121905450172211200?lang=ar
Of course there are always details, and it's possible the precise way Intel insisted on using cobalt (in terms of liners, seeds, temperature processing, etc) got something wrong.
So if cobalt works, why the reversion (or sideways move) to "enhanced copper" (which as I've pointed out before appears to be based on a TSMC paper from, I think it was, 2010)?
This isn't the paper I had in mind (which I can't find right now) but shows similar sort of work: https://ieeexplore.ieee.org/abstract/document/5510762
Perhaps "enhanced copper" was always the optimal solution, it just took time for Intel (and TSMC? or LAM for both of them?) to figure out the metallurgy in enough detail for manufacturing?
> > There has been much speculation about whether the choice of cobalt had something to do
> > with the shortcomings of the 10 nm Intel CMOS process. The fact that Intel 4 has reverted
> > to copper, even if with improved linings, seems to confirm that supposition.
> >
> > The high resistance of the cobalt interconnections is likely to have been one of
> > the reasons for the much too low clock frequencies of Cannon Lake and Ice Lake.
>
> Define "much too low".
>
> Sure, e.g. 3.2 for CNL wasn't king of the hill... but for a U part? Not too bad.
>
> The GPU side... was abysmal though...
>
> Also, if Co was a speed limiter, then Intel should have seen that coming.
> Or are you suggesting their engineers are complete idiots? :)
>
> > The other serious problem of the 10 nm process, the very
> > low yields, might have been determined mainly by their
> > choices for photolithography, where they have attempted to get very small pitches without using EUV.
>
> This.
Yeah, the cobalt story has always seemed like it omitted something.
TSMC use cobalt for 7nm (and presumably 5nm, though I haven't seen direct evidence of that), and did not appear to have problems.
https://twitter.com/lasserith/status/1121905450172211200?lang=ar
Of course there are always details, and it's possible the precise way Intel insisted on using cobalt (in terms of liners, seeds, temperature processing, etc) got something wrong.
So if cobalt works, why the reversion (or sideways move) to "enhanced copper" (which as I've pointed out before appears to be based on a TSMC paper from, I think it was, 2010)?
This isn't the paper I had in mind (which I can't find right now) but shows similar sort of work: https://ieeexplore.ieee.org/abstract/document/5510762
Perhaps "enhanced copper" was always the optimal solution, it just took time for Intel (and TSMC? or LAM for both of them?) to figure out the metallurgy in enough detail for manufacturing?