By: anonymou5 (no.delete@this.spam.com), June 13, 2022 11:50 am
Room: Moderated Discussions
Björn Ragnar Björnsson (bjorn.ragnar.delete@this.gmail.com) on June 13, 2022 9:08 am wrote:
> Does anyone know whether Intel could have gotten acceptable yields when they were struggling
> with their 10nm/Intel 7 process for any part of a SOC? I'm asking: if they'd had their tile/chiplet
> tech done could they have had good yields for certain types of tiles?
>
> Just curious.
CNL-U/Y was just over 70 mm^2, and it did not yield well. So... probably not.
> Does anyone know whether Intel could have gotten acceptable yields when they were struggling
> with their 10nm/Intel 7 process for any part of a SOC? I'm asking: if they'd had their tile/chiplet
> tech done could they have had good yields for certain types of tiles?
>
> Just curious.
CNL-U/Y was just over 70 mm^2, and it did not yield well. So... probably not.