New article: Intel 4 Process Scales Logic with Design, Materials, and EUV

Article: Intel 4 Process Scales Logic with Design, Materials, and EUV
By: Fred Chen (chen.t.fred.delete@this.gmail.com), June 13, 2022 6:11 pm
Room: Moderated Discussions
David Kanter (dkanter.delete@this.realworldtech.com) on June 13, 2022 9:41 am wrote:
> Fred Chen (chen.t.fred.delete@this.gmail.com) on June 13, 2022 8:38 am wrote:
> > David Kanter (dkanter.delete@this.realworldtech.com) on June 12, 2022 7:05 pm wrote:
> > > Hi Everyone,
> > >
> > > Happy Sunday! I am thrilled to bring you my latest article, which focuses on the Intel
> > > 4 process that was presented at the VLSI Symposium in Hawaii. Here's a quick summary:
> > >
> > > The Intel 4 process achieves 20% better performance and scales logic density by 2X while reducing costs
> > > through extensive design co-optimization, adoption of new materials, and judicious use of EUV lithography.
> > > The first product, the Meteor Lake compute tile will ramp to high volume manufacturing in 2023.
> > >
> > > Read more here: Intel 4 Process Scales Logic with Design, Materials, and EUV
> > >
> > > And as always, feel free to discuss or drop questions in this thread!
> > >
> > > David
> > >
> >
> > Nice summary, David, thanks.
>
> Thanks Fred - I appreciate it! I love reading your posts btw.

Thanks for your support!

>
> > One thing that surprised me about Intel 7 was that they used SAQP or pitch quartering on
> > layers which I thought only needed SADP or pitch halving. This was gate as well as M0.
>
> Did they mention where they used SAQP aside from M0?
>
> M0 is 30nm pitch and would require SAQP; I don't see how you could get away with SADP.

I was referring to Intel 7 (10nm) which had M0 40 nm pitch and gate 54 nm pitch. These I would have thought to be SADP. But an Intel paper also mentioned pitch quartering even for the 10nm SF gate.

>
> Did you make it to hawaii?

No I'm still in TW.

Fred
< Previous Post in ThreadNext Post in Thread >
TopicPosted ByDate
New article: Intel 4 Process Scales Logic with Design, Materials, and EUVDavid Kanter2022/06/12 07:05 PM
  New article: Intel 4 Process Scales Logic with Design, Materials, and EUVDylanP2022/06/12 09:52 PM
  New article: Intel 4 Process Scales Logic with Design, Materials, and EUVRohit Garg2022/06/13 12:59 AM
    New article: Intel 4 Process Scales Logic with Design, Materials, and EUVAdrian2022/06/13 01:35 AM
  New article: Intel 4 Process Scales Logic with Design, Materials, and EUVAdrian2022/06/13 01:50 AM
    New article: Intel 4 Process Scales Logic with Design, Materials, and EUVanonymou52022/06/13 06:21 AM
      New article: Intel 4 Process Scales Logic with Design, Materials, and EUVAdrian2022/06/13 07:32 AM
      New article: Intel 4 Process Scales Logic with Design, Materials, and EUV---2022/06/13 10:47 AM
        New article: Intel 4 Process Scales Logic with Design, Materials, and EUVMichael S2022/06/13 11:20 AM
          New article: Intel 4 Process Scales Logic with Design, Materials, and EUV---2022/06/13 09:11 PM
            New article: Intel 4 Process Scales Logic with Design, Materials, and EUVAdrian2022/06/13 10:42 PM
              New article: Intel 4 Process Scales Logic with Design, Materials, and EUV---2022/06/14 09:58 AM
                New article: Intel 4 Process Scales Logic with Design, Materials, and EUVAdrian2022/06/14 12:06 PM
                  New article: Intel 4 Process Scales Logic with Design, Materials, and EUVanonymou52022/06/14 09:25 PM
        New article: Intel 4 Process Scales Logic with Design, Materials, and EUVDavid Kanter2022/06/13 07:26 PM
          New article: Intel 4 Process Scales Logic with Design, Materials, and EUV---2022/06/13 09:08 PM
  Power and Frequency Improvement of Intel 4Sean M2022/06/13 03:28 AM
    Power and Frequency Improvement of Intel 4Adrian2022/06/13 05:27 AM
  Cong is dead, long live eCungMichael S2022/06/13 04:47 AM
  foundry nodesMichael S2022/06/13 05:13 AM
    foundry nodesRayla2022/06/13 05:56 AM
      foundry nodesMichael S2022/06/13 06:20 AM
        foundry nodesRayla2022/06/13 07:24 AM
      foundry nodesanonymou52022/06/13 06:26 AM
  New article: Intel 4 Process Scales Logic with Design, Materials, and EUVFred Chen2022/06/13 08:38 AM
    New article: Intel 4 Process Scales Logic with Design, Materials, and EUVDavid Kanter2022/06/13 09:41 AM
      New article: Intel 4 Process Scales Logic with Design, Materials, and EUVFred Chen2022/06/13 06:11 PM
  New article: Intel 4 Process Scales Logic with Design, Materials, and EUVBjörn Ragnar Björnsson2022/06/13 09:08 AM
    New article: Intel 4 Process Scales Logic with Design, Materials, and EUVanonymou52022/06/13 11:50 AM
    New article: Intel 4 Process Scales Logic with Design, Materials, and EUVBill K2022/06/14 01:58 AM
      [quibble] Yield is not determined by size alonePaul A. Clayton2022/06/14 12:27 PM
        You can always add redundancy ... it is only money!Mark Roulo2022/06/14 01:56 PM
          You can always add redundancy ... it is only money!me2022/06/14 06:11 PM
            You can always add redundancy ... it is only money!anonymou52022/06/14 09:44 PM
              You can always add redundancy ... it is only money!John2022/06/15 04:34 PM
                You can always add redundancy ... it is only money!anonymou52022/06/15 07:09 PM
          You can always add redundancy ... it is only money!Paul A. Clayton2022/06/16 01:04 PM
        [quibble] Yield is not determined by size aloneBill K2022/06/14 02:52 PM
          Yield vs function...Björn Ragnar Björnsson2022/06/14 04:20 PM
            Yield vs function...Bill K2022/06/14 05:33 PM
  New article: Intel 4 Process Scales Logic with Design, Materials, and EUVanon2022/06/21 09:59 AM
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