David Kanter (dkanter.delete@this.realworldtech.com) on June 13, 2022 9:41 am wrote:
> Fred Chen (chen.t.fred.delete@this.gmail.com) on June 13, 2022 8:38 am wrote:
> > David Kanter (dkanter.delete@this.realworldtech.com) on June 12, 2022 7:05 pm wrote:
> > > Hi Everyone,
> > >
> > > Happy Sunday! I am thrilled to bring you my latest article, which focuses on the Intel
> > > 4 process that was presented at the VLSI Symposium in Hawaii. Here's a quick summary:
> > >
> > > The Intel 4 process achieves 20% better performance and scales logic density by 2X while reducing costs
> > > through extensive design co-optimization, adoption of new materials, and judicious use of EUV lithography.
> > > The first product, the Meteor Lake compute tile will ramp to high volume manufacturing in 2023.
> > >
> > > Read more here: Intel 4 Process Scales Logic with Design, Materials, and EUV
> > >
> > > And as always, feel free to discuss or drop questions in this thread!
> > >
> > > David
> > >
> >
> > Nice summary, David, thanks.
>
> Thanks Fred - I appreciate it! I love reading your posts btw.

Thanks for your support!

>
> > One thing that surprised me about Intel 7 was that they used SAQP or pitch quartering on
> > layers which I thought only needed SADP or pitch halving. This was gate as well as M0.
>
> Did they mention where they used SAQP aside from M0?
>
> M0 is 30nm pitch and would require SAQP; I don't see how you could get away with SADP.

I was referring to Intel 7 (10nm) which had M0 40 nm pitch and gate 54 nm pitch. These I would have thought to be SADP. But an Intel paper also mentioned pitch quartering even for the 10nm SF gate.

>
> Did you make it to hawaii?

No I'm still in TW.

Fred