By: --- (---.delete@this.redheron.com), June 13, 2022 9:11 pm
Room: Moderated Discussions
Michael S (already5chosen.delete@this.yahoo.com) on June 13, 2022 11:20 am wrote:
> --- (---.delete@this.redheron.com) on June 13, 2022 10:47 am wrote:
> > anonymou5 (no.delete@this.spam.com) on June 13, 2022 6:21 am wrote:
> > > > There has been much speculation about whether the choice of cobalt had something to do
> > > > with the shortcomings of the 10 nm Intel CMOS process. The fact that Intel 4 has reverted
> > > > to copper, even if with improved linings, seems to confirm that supposition.
> > > >
> > > > The high resistance of the cobalt interconnections is likely to have been one of
> > > > the reasons for the much too low clock frequencies of Cannon Lake and Ice Lake.
> > >
> > > Define "much too low".
> > >
> > > Sure, e.g. 3.2 for CNL wasn't king of the hill... but for a U part? Not too bad.
> > >
> > > The GPU side... was abysmal though...
> > >
> > > Also, if Co was a speed limiter, then Intel should have seen that coming.
> > > Or are you suggesting their engineers are complete idiots? :)
> > >
> > > > The other serious problem of the 10 nm process, the very
> > > > low yields, might have been determined mainly by their
> > > > choices for photolithography, where they have attempted to get very small pitches without using EUV.
> > >
> > > This.
> >
> > Yeah, the cobalt story has always seemed like it omitted something.
> > TSMC use cobalt for 7nm (and presumably 5nm, though I haven't seen
> > direct evidence of that), and did not appear to have problems.
> > https://twitter.com/lasserith/status/1121905450172211200?lang=ar
> >
>
> The tweet is bragging about cobalt *contacts*.
> Intel tried to use cobalt *conductors* instead of copper conductors in two inner layers of the stack.
I don't know if "bragging" is the right word...
You know where Moshe works, don't you?
The distinction between contacts and layers is a reasonable point, but is it significant?
Is there an interest/important reason why it's more difficult to create a layer of cobalt traces than to create short vertical contacts of cobalt? I guess there is *some* difference given that tungsten has frequently been used for these sorts of plugs, but I'd love to know the full story.
> --- (---.delete@this.redheron.com) on June 13, 2022 10:47 am wrote:
> > anonymou5 (no.delete@this.spam.com) on June 13, 2022 6:21 am wrote:
> > > > There has been much speculation about whether the choice of cobalt had something to do
> > > > with the shortcomings of the 10 nm Intel CMOS process. The fact that Intel 4 has reverted
> > > > to copper, even if with improved linings, seems to confirm that supposition.
> > > >
> > > > The high resistance of the cobalt interconnections is likely to have been one of
> > > > the reasons for the much too low clock frequencies of Cannon Lake and Ice Lake.
> > >
> > > Define "much too low".
> > >
> > > Sure, e.g. 3.2 for CNL wasn't king of the hill... but for a U part? Not too bad.
> > >
> > > The GPU side... was abysmal though...
> > >
> > > Also, if Co was a speed limiter, then Intel should have seen that coming.
> > > Or are you suggesting their engineers are complete idiots? :)
> > >
> > > > The other serious problem of the 10 nm process, the very
> > > > low yields, might have been determined mainly by their
> > > > choices for photolithography, where they have attempted to get very small pitches without using EUV.
> > >
> > > This.
> >
> > Yeah, the cobalt story has always seemed like it omitted something.
> > TSMC use cobalt for 7nm (and presumably 5nm, though I haven't seen
> > direct evidence of that), and did not appear to have problems.
> > https://twitter.com/lasserith/status/1121905450172211200?lang=ar
> >
>
> The tweet is bragging about cobalt *contacts*.
> Intel tried to use cobalt *conductors* instead of copper conductors in two inner layers of the stack.
I don't know if "bragging" is the right word...
You know where Moshe works, don't you?
The distinction between contacts and layers is a reasonable point, but is it significant?
Is there an interest/important reason why it's more difficult to create a layer of cobalt traces than to create short vertical contacts of cobalt? I guess there is *some* difference given that tungsten has frequently been used for these sorts of plugs, but I'd love to know the full story.
