By: Bill K (bill.delete@this.gmail.com), June 14, 2022 1:58 am
Room: Moderated Discussions
> Does anyone know whether Intel could have gotten acceptable yields when they were struggling with their 10nm/Intel 7 process
> for any part of a SOC? I'm asking: if they'd had their tile/chiplet tech done could they have had good yields for certain types of tiles?
Yes, if the tiles were small enough. The lower the yields are, the smaller the tiles would need to be. In Q1 2022, Intel shipped 15M Alder Lake client processors, which are on Intel 7. There are two versions of Adler Lake, one with a die size of 163 mm^2 and the other with a die size of 215 mm^2. Apparently, Intel is currently able to manufacture this die size successfully on Intel 7.
The Sapphire Rapids Xeon has 4 tiles that are 400 mm^2 each on Intel 7. For comparison, each of the 12 CPU tiles in AMD’s Genoa processor are 72 mm^2 on TSMC 5nm. The non-HBM Sapphire Rapids was recently delayed to Q4 2022 and the HBM Sapphire Rapids was delayed to the first half of 2023.
> for any part of a SOC? I'm asking: if they'd had their tile/chiplet tech done could they have had good yields for certain types of tiles?
Yes, if the tiles were small enough. The lower the yields are, the smaller the tiles would need to be. In Q1 2022, Intel shipped 15M Alder Lake client processors, which are on Intel 7. There are two versions of Adler Lake, one with a die size of 163 mm^2 and the other with a die size of 215 mm^2. Apparently, Intel is currently able to manufacture this die size successfully on Intel 7.
The Sapphire Rapids Xeon has 4 tiles that are 400 mm^2 each on Intel 7. For comparison, each of the 12 CPU tiles in AMD’s Genoa processor are 72 mm^2 on TSMC 5nm. The non-HBM Sapphire Rapids was recently delayed to Q4 2022 and the HBM Sapphire Rapids was delayed to the first half of 2023.
