[quibble] Yield is not determined by size alone

Article: Intel 4 Process Scales Logic with Design, Materials, and EUV
By: Paul A. Clayton (paaronclayton.delete@this.gmail.com), June 14, 2022 12:27 pm
Room: Moderated Discussions
Bill K (bill.delete@this.gmail.com) on June 14, 2022 1:58 am wrote:
> > Does anyone know whether Intel could have gotten acceptable yields
> > when they were struggling with their 10nm/Intel 7 process
> > for any part of a SOC? I'm asking: if they'd had their tile/chiplet tech
> > done could they have had good yields for certain types of tiles?
>
> Yes, if the tiles were small enough. The lower the yields are, the smaller the tiles would need to
> be.

Redundancy can provide reasonable yields even with somewhat high defect rates. Even for memory arrays, the locality of defects/extreme variation can bias whether row/column spares or array spares are more attractive.

A machine learning matrix processor could have significant defect tolerance (the cost of modestly more complex routing around defective components is less important for more throughput-oriented designs).

Even a conventional great-big-out-of-order processor could support redundant simple functional units (and possibly redundancy in a multiplier array) at some cost in latency from additional routing complexity and many parts of the processor are N identical/very similar blocks (though the smallish N for schedulers increases the fraction of lost functionality and the overhead for control/routing).

There may also be process variation which makes a working device too slow to be marketable, but this boundary is dependent on the product target. (Presumably there are also power/performance/area tradeoffs that can be made at design time to improve yield. Choosing a "worse" process with lower defect rates may usually be financially sensible rather than sacrificing PPA in design for yield, but much of the pricing is based on competition [if the fixed costs are taken as a loss and some of the incremental costs are allocated to research-and-development — assuming active production facilitates learning — the pricing of a broken process may be low yet the process still be made available; the pricing of a donation to a university research project might also be difficult to define].)

(I am not an EE or financial analyst, but these seem reasonable inferences from broad principles.)
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New article: Intel 4 Process Scales Logic with Design, Materials, and EUVDavid Kanter2022/06/12 07:05 PM
  New article: Intel 4 Process Scales Logic with Design, Materials, and EUVDylanP2022/06/12 09:52 PM
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      New article: Intel 4 Process Scales Logic with Design, Materials, and EUVAdrian2022/06/13 07:32 AM
      New article: Intel 4 Process Scales Logic with Design, Materials, and EUV---2022/06/13 10:47 AM
        New article: Intel 4 Process Scales Logic with Design, Materials, and EUVMichael S2022/06/13 11:20 AM
          New article: Intel 4 Process Scales Logic with Design, Materials, and EUV---2022/06/13 09:11 PM
            New article: Intel 4 Process Scales Logic with Design, Materials, and EUVAdrian2022/06/13 10:42 PM
              New article: Intel 4 Process Scales Logic with Design, Materials, and EUV---2022/06/14 09:58 AM
                New article: Intel 4 Process Scales Logic with Design, Materials, and EUVAdrian2022/06/14 12:06 PM
                  New article: Intel 4 Process Scales Logic with Design, Materials, and EUVanonymou52022/06/14 09:25 PM
        New article: Intel 4 Process Scales Logic with Design, Materials, and EUVDavid Kanter2022/06/13 07:26 PM
          New article: Intel 4 Process Scales Logic with Design, Materials, and EUV---2022/06/13 09:08 PM
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      foundry nodesMichael S2022/06/13 06:20 AM
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  New article: Intel 4 Process Scales Logic with Design, Materials, and EUVFred Chen2022/06/13 08:38 AM
    New article: Intel 4 Process Scales Logic with Design, Materials, and EUVDavid Kanter2022/06/13 09:41 AM
      New article: Intel 4 Process Scales Logic with Design, Materials, and EUVFred Chen2022/06/13 06:11 PM
  New article: Intel 4 Process Scales Logic with Design, Materials, and EUVBjörn Ragnar Björnsson2022/06/13 09:08 AM
    New article: Intel 4 Process Scales Logic with Design, Materials, and EUVanonymou52022/06/13 11:50 AM
    New article: Intel 4 Process Scales Logic with Design, Materials, and EUVBill K2022/06/14 01:58 AM
      [quibble] Yield is not determined by size alonePaul A. Clayton2022/06/14 12:27 PM
        You can always add redundancy ... it is only money!Mark Roulo2022/06/14 01:56 PM
          You can always add redundancy ... it is only money!me2022/06/14 06:11 PM
            You can always add redundancy ... it is only money!anonymou52022/06/14 09:44 PM
              You can always add redundancy ... it is only money!John2022/06/15 04:34 PM
                You can always add redundancy ... it is only money!anonymou52022/06/15 07:09 PM
          You can always add redundancy ... it is only money!Paul A. Clayton2022/06/16 01:04 PM
        [quibble] Yield is not determined by size aloneBill K2022/06/14 02:52 PM
          Yield vs function...Björn Ragnar Björnsson2022/06/14 04:20 PM
            Yield vs function...Bill K2022/06/14 05:33 PM
  New article: Intel 4 Process Scales Logic with Design, Materials, and EUVanon2022/06/21 09:59 AM
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