By: Bill K (bill.delete@this.gmail.com), June 14, 2022 2:52 pm
Room: Moderated Discussions
I agree. Roughly 1/3 to 1/2 the chip area in a Xeon processor is memory and redundancy can easily be used for that. Sapphire Rapids has a total L2+L3 cache size of 280 MBytes. Similar to what Mark Roulo described for the Nvidia A100, each of the four 400 mm^2 Sapphire Rapids tiles contain 15 CPU cores. When some CPU cores are defective, Intel can sell the device as a different part number. The maximum number of CPU cores Intel will enable per tile is 14.
Changing the subject, the thermal design power of the 56 core Sapphire Rapids is 350W and the maximum turbo power is 420W. Intel 4 is needed to improve these numbers, protect the polar bears and compete with AMD on performance per Watt.
Changing the subject, the thermal design power of the 56 core Sapphire Rapids is 350W and the maximum turbo power is 420W. Intel 4 is needed to improve these numbers, protect the polar bears and compete with AMD on performance per Watt.