Yield vs function...

Article: Intel 4 Process Scales Logic with Design, Materials, and EUV
By: Björn Ragnar Björnsson (bjorn.ragnar.delete@this.gmail.com), June 14, 2022 3:20 pm
Room: Moderated Discussions
Bill K (bill.delete@this.gmail.com) on June 14, 2022 2:52 pm wrote:
> I agree. Roughly 1/3 to 1/2 the chip area in a Xeon processor is memory and redundancy can easily
> be used for that. Sapphire Rapids has a total L2+L3 cache size of 280 MBytes. Similar to what
> Mark Roulo described for the Nvidia A100, each of the four 400 mm^2 Sapphire Rapids tiles contain
> 15 CPU cores. When some CPU cores are defective, Intel can sell the device as a different part
> number. The maximum number of CPU cores Intel will enable per tile is 14.
>
> Changing the subject, the thermal design power of the 56 core Sapphire Rapids
> is 350W and the maximum turbo power is 420W. Intel 4 is needed to improve these
> numbers, protect the polar bears and compete with AMD on performance per Watt.

Thank you all for your informative answers. Going to chiplet/tile configuration is of course automatically going to lead to smaller dies (ceteris paribus) and therefore higher yields (at some cost in performance and/or complexity/packaging costs). I was particularly interested in whether there was a difference in defect rates per area in Intel 7 comparing say Core+Cache vs rest of the SOC.
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New article: Intel 4 Process Scales Logic with Design, Materials, and EUVDavid Kanter2022/06/12 06:05 PM
  New article: Intel 4 Process Scales Logic with Design, Materials, and EUVDylanP2022/06/12 08:52 PM
  New article: Intel 4 Process Scales Logic with Design, Materials, and EUVRohit Garg2022/06/12 11:59 PM
    New article: Intel 4 Process Scales Logic with Design, Materials, and EUVAdrian2022/06/13 12:35 AM
  New article: Intel 4 Process Scales Logic with Design, Materials, and EUVAdrian2022/06/13 12:50 AM
    New article: Intel 4 Process Scales Logic with Design, Materials, and EUVanonymou52022/06/13 05:21 AM
      New article: Intel 4 Process Scales Logic with Design, Materials, and EUVAdrian2022/06/13 06:32 AM
      New article: Intel 4 Process Scales Logic with Design, Materials, and EUV---2022/06/13 09:47 AM
        New article: Intel 4 Process Scales Logic with Design, Materials, and EUVMichael S2022/06/13 10:20 AM
          New article: Intel 4 Process Scales Logic with Design, Materials, and EUV---2022/06/13 08:11 PM
            New article: Intel 4 Process Scales Logic with Design, Materials, and EUVAdrian2022/06/13 09:42 PM
              New article: Intel 4 Process Scales Logic with Design, Materials, and EUV---2022/06/14 08:58 AM
                New article: Intel 4 Process Scales Logic with Design, Materials, and EUVAdrian2022/06/14 11:06 AM
                  New article: Intel 4 Process Scales Logic with Design, Materials, and EUVanonymou52022/06/14 08:25 PM
        New article: Intel 4 Process Scales Logic with Design, Materials, and EUVDavid Kanter2022/06/13 06:26 PM
          New article: Intel 4 Process Scales Logic with Design, Materials, and EUV---2022/06/13 08:08 PM
  Power and Frequency Improvement of Intel 4Sean M2022/06/13 02:28 AM
    Power and Frequency Improvement of Intel 4Adrian2022/06/13 04:27 AM
  Cong is dead, long live eCungMichael S2022/06/13 03:47 AM
  foundry nodesMichael S2022/06/13 04:13 AM
    foundry nodesRayla2022/06/13 04:56 AM
      foundry nodesMichael S2022/06/13 05:20 AM
        foundry nodesRayla2022/06/13 06:24 AM
      foundry nodesanonymou52022/06/13 05:26 AM
  New article: Intel 4 Process Scales Logic with Design, Materials, and EUVFred Chen2022/06/13 07:38 AM
    New article: Intel 4 Process Scales Logic with Design, Materials, and EUVDavid Kanter2022/06/13 08:41 AM
      New article: Intel 4 Process Scales Logic with Design, Materials, and EUVFred Chen2022/06/13 05:11 PM
  New article: Intel 4 Process Scales Logic with Design, Materials, and EUVBjörn Ragnar Björnsson2022/06/13 08:08 AM
    New article: Intel 4 Process Scales Logic with Design, Materials, and EUVanonymou52022/06/13 10:50 AM
    New article: Intel 4 Process Scales Logic with Design, Materials, and EUVBill K2022/06/14 12:58 AM
      [quibble] Yield is not determined by size alonePaul A. Clayton2022/06/14 11:27 AM
        You can always add redundancy ... it is only money!Mark Roulo2022/06/14 12:56 PM
          You can always add redundancy ... it is only money!me2022/06/14 05:11 PM
            You can always add redundancy ... it is only money!anonymou52022/06/14 08:44 PM
              You can always add redundancy ... it is only money!John2022/06/15 03:34 PM
                You can always add redundancy ... it is only money!anonymou52022/06/15 06:09 PM
          You can always add redundancy ... it is only money!Paul A. Clayton2022/06/16 12:04 PM
        [quibble] Yield is not determined by size aloneBill K2022/06/14 01:52 PM
          Yield vs function...Björn Ragnar Björnsson2022/06/14 03:20 PM
            Yield vs function...Bill K2022/06/14 04:33 PM
              Yield vs function...tacobell2022/08/06 04:51 AM
  New article: Intel 4 Process Scales Logic with Design, Materials, and EUVanon2022/06/21 08:59 AM
  New article: Intel 4 Process Scales Logic with Design, Materials, and EUVtacobell2022/08/06 04:39 AM
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