By: Bill K (bill.delete@this.gmail.com), June 14, 2022 5:33 pm
Room: Moderated Discussions
> I was particularly interested in whether there was a difference in defect rates
> per area in Intel 7 comparing say Core+Cache vs rest of the SOC.
I suppose it’s possible that the higher-voltage transistors, mixed-signal tranceivers and I/O pads could have a different defect density than the core+cache. My guess would be no because most of that area (DRAM controllers, PCIe controllers, Compute Express Link, Ultra Path Interconnect) is logic that will have a similar defect density to logic in the CPU core. A defect in a DRAM controller would make a tile unsellable because there are no part numbers with different numbers of DRAM controllers per tile. So it’s much worse to have a defect in a DRAM controller than a CPU core, even if the defect density in both are the same.
> per area in Intel 7 comparing say Core+Cache vs rest of the SOC.
I suppose it’s possible that the higher-voltage transistors, mixed-signal tranceivers and I/O pads could have a different defect density than the core+cache. My guess would be no because most of that area (DRAM controllers, PCIe controllers, Compute Express Link, Ultra Path Interconnect) is logic that will have a similar defect density to logic in the CPU core. A defect in a DRAM controller would make a tile unsellable because there are no part numbers with different numbers of DRAM controllers per tile. So it’s much worse to have a defect in a DRAM controller than a CPU core, even if the defect density in both are the same.
