You can always add redundancy ... it is only money!

Article: Intel 4 Process Scales Logic with Design, Materials, and EUV
By: Paul A. Clayton (paaronclayton.delete@this.gmail.com), June 16, 2022 1:04 pm
Room: Moderated Discussions
Mark Roulo (nothanks.delete@this.xxx.com) on June 14, 2022 1:56 pm wrote:
> Paul A. Clayton (paaronclayton.delete@this.gmail.com) on June 14, 2022 12:27 pm wrote:

[snip]

>> Redundancy can provide reasonable yields even with somewhat
>> high defect rates. Even for memory arrays, the locality
>> of defects/extreme variation can bias whether row/column spares or array spares are more attractive.

[snip]

> In theory one can make a design/implementation which is AMAZINGLY robust
> against manufacturing defects. Triply (or more) redundant everything.
>
> Though this would likely lead to worse performance.

Even the much more modest redundancy (N+1 for many structures beyond memory arrays, possibly even N+2) I mentioned would have had performance costs — and I also mentioned the possibility of sacrificing performance and power for manufacturability — increasing area will increase communication latency and opportunity for clock skew (and possibly jitter?). Even the design effort will cost performance.

(Margin for variability also impacts yield. Frequency binning is one technique available, but — if I understand correctly — low- and intermediate-level design can increase tolerance for variability at the cost of area, power, performance, and design effort. Similarly, performance et al. can be tweaked by sacrificing yield. With high mask set costs, a low-volume product might generate more profit with higher performance but lower yield.)

> In practice, folks are already providing redundancy where it is practical.

Where it is practical depends on a process' variability and defect rate and the design/market goals for the product. Non-foundry Intel had more opportunity to shift costs between the process, low-level design, and even (somewhat) product target. The accounting, as I implied, could be even less clearly segmented.

> Memory regions are a good example of this (standalone DRAM and FLASH as well as caches).

I was under the impression that column (row?) based redundancy was standard for SRAM arrays. Array-level redundancy was used by one of the Itanium implementations and presumably would make sense in some circumstances.

[snip]

> Notice that NVidia is losing a full 15% of their manufactured FLOPS just to allow the part to work.
>
> NVidia gets away with this because the margins on the A100 chips are very
> high. But this is probably a bad plan for laptop and desktop chips.

Even for lower-margin chips, 15% area cost is not necessarily that important if one is gaining effectively 80% more area (with possible integration benefits) from a new process and gaining performance and power benefits from that process.

Obviously a GPU or sea-of-cores design can more trivially exploit coarse-grained redundancy (which will have less impact on local latency). For Intel, leading in performance or energy efficiency is important for brand reasons, so finer-grained redundancy may be especially unattractive (and even in the personal computer processor market, binning can complicate power-performance-area-yield decisions). If one knows well in advance that all of one's product will be produced in

(Radiation tolerance — and tolerance to other "environmental" factors, including temperature and voltage stability — would seem to also interact with design for manufacturing variability/defectivity. This implies that the tradeoffs might be significantly different for different products.)

Design effort and changing design orientation will also introduce risk, so one would not expect universal adoption of different methods even within one organization.

If defectivity/variation was unexpectedly high and persistent (possibly even from trying to tweak a process to improve performance or energy efficiency), the designs ready for this new cost structure would not be suited to the unexpected tradeoffs.

If the information was available, the design space for manufacturability tradeoffs with fixed and incremental costs and product value (performance, energy efficiency) might be a good PhD thesis topic — or more likely long-term research interest.
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New article: Intel 4 Process Scales Logic with Design, Materials, and EUVDavid Kanter2022/06/12 07:05 PM
  New article: Intel 4 Process Scales Logic with Design, Materials, and EUVDylanP2022/06/12 09:52 PM
  New article: Intel 4 Process Scales Logic with Design, Materials, and EUVRohit Garg2022/06/13 12:59 AM
    New article: Intel 4 Process Scales Logic with Design, Materials, and EUVAdrian2022/06/13 01:35 AM
  New article: Intel 4 Process Scales Logic with Design, Materials, and EUVAdrian2022/06/13 01:50 AM
    New article: Intel 4 Process Scales Logic with Design, Materials, and EUVanonymou52022/06/13 06:21 AM
      New article: Intel 4 Process Scales Logic with Design, Materials, and EUVAdrian2022/06/13 07:32 AM
      New article: Intel 4 Process Scales Logic with Design, Materials, and EUV---2022/06/13 10:47 AM
        New article: Intel 4 Process Scales Logic with Design, Materials, and EUVMichael S2022/06/13 11:20 AM
          New article: Intel 4 Process Scales Logic with Design, Materials, and EUV---2022/06/13 09:11 PM
            New article: Intel 4 Process Scales Logic with Design, Materials, and EUVAdrian2022/06/13 10:42 PM
              New article: Intel 4 Process Scales Logic with Design, Materials, and EUV---2022/06/14 09:58 AM
                New article: Intel 4 Process Scales Logic with Design, Materials, and EUVAdrian2022/06/14 12:06 PM
                  New article: Intel 4 Process Scales Logic with Design, Materials, and EUVanonymou52022/06/14 09:25 PM
        New article: Intel 4 Process Scales Logic with Design, Materials, and EUVDavid Kanter2022/06/13 07:26 PM
          New article: Intel 4 Process Scales Logic with Design, Materials, and EUV---2022/06/13 09:08 PM
  Power and Frequency Improvement of Intel 4Sean M2022/06/13 03:28 AM
    Power and Frequency Improvement of Intel 4Adrian2022/06/13 05:27 AM
  Cong is dead, long live eCungMichael S2022/06/13 04:47 AM
  foundry nodesMichael S2022/06/13 05:13 AM
    foundry nodesRayla2022/06/13 05:56 AM
      foundry nodesMichael S2022/06/13 06:20 AM
        foundry nodesRayla2022/06/13 07:24 AM
      foundry nodesanonymou52022/06/13 06:26 AM
  New article: Intel 4 Process Scales Logic with Design, Materials, and EUVFred Chen2022/06/13 08:38 AM
    New article: Intel 4 Process Scales Logic with Design, Materials, and EUVDavid Kanter2022/06/13 09:41 AM
      New article: Intel 4 Process Scales Logic with Design, Materials, and EUVFred Chen2022/06/13 06:11 PM
  New article: Intel 4 Process Scales Logic with Design, Materials, and EUVBjörn Ragnar Björnsson2022/06/13 09:08 AM
    New article: Intel 4 Process Scales Logic with Design, Materials, and EUVanonymou52022/06/13 11:50 AM
    New article: Intel 4 Process Scales Logic with Design, Materials, and EUVBill K2022/06/14 01:58 AM
      [quibble] Yield is not determined by size alonePaul A. Clayton2022/06/14 12:27 PM
        You can always add redundancy ... it is only money!Mark Roulo2022/06/14 01:56 PM
          You can always add redundancy ... it is only money!me2022/06/14 06:11 PM
            You can always add redundancy ... it is only money!anonymou52022/06/14 09:44 PM
              You can always add redundancy ... it is only money!John2022/06/15 04:34 PM
                You can always add redundancy ... it is only money!anonymou52022/06/15 07:09 PM
          You can always add redundancy ... it is only money!Paul A. Clayton2022/06/16 01:04 PM
        [quibble] Yield is not determined by size aloneBill K2022/06/14 02:52 PM
          Yield vs function...Björn Ragnar Björnsson2022/06/14 04:20 PM
            Yield vs function...Bill K2022/06/14 05:33 PM
  New article: Intel 4 Process Scales Logic with Design, Materials, and EUVanon2022/06/21 09:59 AM
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