Doug S (foo.delete@this.bar.bar) on June 16, 2022 9:39 am wrote:
> hobold (hobold.delete@this.vectorizer.org) on June 16, 2022 5:12 am wrote:
[snip]
>> I was wondering for a while if maybe Apple designed a processor that can sometimes
>> execute two serially dependent instructions within one longer clock cycle.
>>
>> How much % of cycle time is latch overhead these days? What if instead of the usual beat
>> "latch work latch work latch" you built for "latch work work latch work work latch"?
>>
>> One probably wouldn't even try to make this work for arbitrary sequences of two dependent instructions.
>> But maybe a small subset of dependent pairs is statistically dominant enough to focus on?
>
> It sounds like you're suggesting something like Pentium
> 4's "double pumped ALU" (aka "Rapid Execution Engine")

The proposal was to remove latch overhead (width-pipelined/staggered ALUs do not remove the latches between operations). A cascaded ALU does perform one operation after another (plausibly without latches). I think Sun's SuperSPARC implemented something like this

> Essentially the ALU was running at double the frequency. According to Intel that was done to make up for
> the Pentium 4's rather anemic IPC. Not sure how it would work on a CPU that already has very high IPC.

Cascaded ALUs can reduce routing overhead (and possibly latch overhead).

> Running at double the frequency (even if it could be managed to enable/disable that
> at a whim, or have only one core doing at a time, etc.) is likely to have negative
> consequences for efficiency, which is one of Apple's primary design goals.

Cascaded ALUs do not target higher frequency; the reduced routing complexity (and possibly larger scheduling window from scheduling at coarser granularity) could provide greater energy efficiency if utilization of the feature was high.

(Even a width-pipelined ALU would not have to target higher frequency and might provide energy efficiency benefits. At the same frequency, a half-width adder would need less logic.)