Sean M (sean.delete@this.none.com) on June 17, 2022 4:18 am wrote:
> --- (---.delete@this.redheron.com) on June 16, 2022 10:53 pm wrote:
> > Let me remind you once again that Apple has ambitions far grander
> > than most people here imagine. Apple was pretty much the platform
> > of choice for the STEM crowd when they were on Intel, and they
> > have every ambition to be back there (along with other goals).
>
> I’m interested in your comment above about Apple’s STEM ambitions. The paragraph
> [0048] in the patent you provided a link for mentions support for page sizes up to 512
> MBytes. The L2 TLB in the M1 has 3072 entries so that would cover 1.5 TBytes with 512
> MByte pages. The maximum DRAM size of the current Mac Pro is also 1.5 TBytes.
>
> Are you saying that since consumers don’t need 1.5 TBytes of DRAM, support for 512 MByte pages
> suggests Apple is interested in STEM applications? Or did you accidently post a link to the wrong
> Apple patent (Reducing Translation Lookaside Buffer Searches for Splintered Pages)?

That's the patent I wanted.
BWT one of the two companion patents filed at the same time strongly suggests that the L2 TLB in a "new" design (perhaps already the A15) will have 4096 entries (256 sets, 16 ways, as opposed to the current 256 sets 12 ways).

The point of interest is not just the huge pages, it's the RANGE of page sizes. Why would a company that has been happy with 16K pages for years now decide that
- it wants to support large pages
- and not just one large page size
- and (most specifically) why THOSE sizes...
What does this capability GET you...

> STEM applications need a lot of 64-bit floating point performance while cell phone applications don’t.
> How do you think Apple will reconcile this difference in requirements? Would it be by putting a lot of 64-bit
> floating point hardware in the AMX block and not including the AMX block in their cell phone chips? Since
> there is only one AMX block per four P-cores, how could that be competitive with dual AXV-512 units with
> fused multiply-adds in every core? Do you think Apple will make two different implementations of SVE2, with
> long hardware vectors in the M series and short hardware vectors in the A series? Does Apple currently support
> floating point fused multiply-adds in NEON, which is an optional ARM NEON extension? Other than this patent,
> have you seen other hints that suggest Apple is interested in STEM applications?

I already posted a month or so ago my analysis of recent AMX activity and how that is being modified from an outer product/matrix product engine to something that can perform a lot of AMX FP heavy lifting.
I have no idea what Apple WILL do, I simply note what I consider to be strong patterns.
The TLB patents, the AMX patents, the new scalable coherency protocol, the packaging patents for substantial (and independent) scaling of cores and DRAM -- none of this work is being done to make faster phones and Macbook Airs. Even the use of Optane (or something similar) as a slow, persistent, but very dense DRAM augmentation, something I thought had ended around 2016 still seems to be ongoing with a recent patent in that space.

I don't believe Apple want to sell a supercomputer based on 2023 Apple Silicon (though they do want to sell a whole lot of these MacBook Pros, to individuals, and Mac Studios to departments, on the strength of these being the best available "cheap" devices for Mathematica, or development, or running a certain degree of large PDE solvers). And if you want hypervisors and Linux within which to run those apps, go right ahead.
And 2033 Apple Silicon for super computers??? I wouldn't rule it out.

But of course the nature of the non-visionary is to refuse to see something until it is literally before their eyes (and then to claim it was obvious all along and no big deal). Pro/Max and the Ultra were both completely unexpected, but still we get people insisting that Ultra "obviously" represents as large as Apple will go. Oh well.