Sam G (samg.delete@this.gmail.com) on June 22, 2022 12:06 am wrote:
> > > There is no mention of ECC in the Tech Specs section of the Mac Studio page on Apple’s website.
> > ECC is problematic to provide with LPDDR.
>
> Micron LPDDR4 and LPDDR4x DRAM includes on-die ECC:
>
> micron.com/about/blog/2017/february/the-advantage-of-ecc-dram-in-smartphones
>
> LPDDR5 has Link-ECC. Inline ECC can be used with both LPDDR4 and LPDDR5 as described here:
>
> semiengineering.com/what-designers-need-to-know-about-error-correction-code-ecc-in-ddr-memories
>
> > It may become more scarce in general with DDR5 since the bit overhead doubles
>
> You’re right about an ECC DDR5 DIMM being 80 bits wide, compared to 72 bits wide for an
> ECC DDR4 DIMM. As you know, this is due to the DDR5 data bus being split into two subchannels.
> All DDR5 DRAMs, whether on an ECC DIMM or a non-ECC DIMM, have on-die ECC, which is an additional
> 6.25% overhead. DRAM sizes are increasing with DDR5 so ECC is more essential.


We just went through a big discussion of this on this forum some months ago. I won't rehash the whole thing, but this type of on die ECC Micron makes available on some LPDDR parts and is included in the DDR5 spec is not remotely close to the capability of standard ECC DIMMs that have been used in servers and high end workstations for years.

Worse, it appears that OEMs may have put the on die ECC spec in the DDR5 standard simply to allow them to ship defective dies (i.e. with errors the internal ECC corrects) so it may not add ANY protection at all. Since there is no way to find out when data is corrected via DDR5's on die ECC, and it does not protect data in transit from the DIMM to the controller, it is basically useless.